Rev. 2.1

May 2000

1/148

This is preliminary information on a new product in development or undergoing evaluation. Details are subject to change without notice.

ST72334J/N,

ST72314J/N, ST72124J

8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY,

ADC, 16-BIT TIMERS, SPI, SCI INTERFACES

PRELIMINARY DATA

Memories

8K or 16K Program memory (ROM or single

voltage FLASH) with read-out protection and

in-situ programming (remote ISP)

256 bytes EEPROM Data memory (with read-

out protection option in ROM devices)

384 or 512 bytes RAM

Clock, Reset and Supply Management

Enhanced reset system
Enhanced low voltage supply supervisor with

3 programmable levels

Clock sources: crystal/ceramic resonator os-

cillators or RC oscillators, external clock,

backup Clock Security System

4 Power Saving Modes: Halt, Active-Halt,

Wait and Slow

Beep and clock-out capabilities

Interrupt Management

10 interrupt vectors plus TRAP and RESET
15 external interrupt lines (4 vectors)

44 or 32 I/O Ports

44 or 32 multifunctional bidirectional I/O lines:
21 or 19 alternate function lines
12 or 8 high sink outputs

4 Timers

Configurable watchdog timer
Realtime base
Two 16-bit timers with: 2 input captures (only

one on timer A), 2 output compares (only one

on timer A), External clock input on timer A,

PWM and Pulse generator modes

2 Communications Interfaces

SPI synchronous serial interface
SCI asynchronous serial interface

1 Analog Peripheral

8-bit ADC with 8 input channels (6 only on

ST72334Jx, not available on ST72124J2)

Instruction Set

8-bit data manipulation
63 basic instructions
17 main addressing modes
8 x 8 unsigned multiply instruction
True bit manipulation

Development Tools

Full hardware/software development package

Device Summary

TQFP44

10 x 10

PSDIP42

PSDIP56

TQFP64

14 x 14

Features

ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4

Program memory - bytes

16K

RAM (stack) - bytes

384 (256)

512 (256)

384 (256)

512 (256)

384 (256)

512 (256)

384 (256)

512 (256)

EEPROM - bytes

256

Peripherals

Watchdog, Two 16-bit Timers, SPI, SCI

ADC

Operating Supply

3.0V to 5.5 V

CPU Frequency

Up to 8 MHz (with up to 16 MHz oscillator)

Operating Temperature

-40

C to +85

C (-40

C to +105/125

C optional)

Packages

TQFP44 / SDIP42

TQFP64 / SDIP56

TQFP44 / SDIP42

TQFP64 / SDIP56

Table of Contents

148

2/148

1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 REGISTER & MEMORY MAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 FLASH PROGRAM MEMORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.3

STRUCTURAL ORGANISATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.4

IN-SITU PROGRAMMING (ISP) MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5

MEMORY READ-OUT PROTECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

6 DATA EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.3

MEMORY ACCESS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

6.4

POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.5

ACCESS ERROR HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

6.6

6.7

READ-OUT PROTECTION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

7 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.1

INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.2

MAIN FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

7.3

CPU REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

8 SUPPLY, RESET AND CLOCK MANAGEMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

8.1

LOW VOLTAGE DETECTOR (LVD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

8.2

RESET SEQUENCE MANAGER (RSM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

8.3

MULTI-OSCILLATOR (MO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

8.4

CLOCK SECURITY SYSTEM (CSS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

8.5

SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 30

9 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.1

NON MASKABLE SOFTWARE INTERRUPT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.2

EXTERNAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

9.3

PERIPHERAL INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

10 POWER SAVING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.2 SLOW MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

10.3 WAIT MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

10.4 ACTIVE-HALT AND HALT MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

11 I/O PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11.1 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11.2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

11.3 I/O PORT IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

11.4 LOW POWER MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Table of Contents

3/148

11.5 INTERRUPTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

12 MISCELLANEOUS REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.1 I/O PORT INTERRUPT SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.2 I/O PORT ALTERNATE FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

12.3 REGISTERS DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

13 ON-CHIP PERIPHERALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.1 WATCHDOG TIMER (WDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

13.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC) . . . . . . . 50

13.3 16-BIT TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

13.4 SERIAL PERIPHERAL INTERFACE (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

13.5 SERIAL COMMUNICATIONS INTERFACE (SCI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

13.6 8-BIT A/D CONVERTER (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

14 INSTRUCTION SET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

14.1 ST7 ADDRESSING MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

14.2 INSTRUCTION GROUPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

15.1 PARAMETER CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

15.2 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

15.3 OPERATING CONDITIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

15.4 SUPPLY CURRENT CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

15.5 CLOCK AND TIMING CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

15.6 MEMORY CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119

15.7 EMC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

15.8 I/O PORT PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

15.9 CONTROL PIN CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128

15.10 TIMER PERIPHERAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

15.11 COMMUNICATION INTERFACE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . 132

15.12 8-BIT ADC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

16 PACKAGE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

16.1 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

16.2 THERMAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

16.3 SOLDERING AND GLUEABILITY INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

16.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141

17 DEVICE CONFIGURATION AND ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . 143

17.1 OPTION BYTES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

17.2 DEVELOPMENT TOOLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

18 SUMMARY OF CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147

ST72334J/N, ST72314J/N, ST72124J

4/148

1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION

New Features available on the ST72C334

16K

FLASH/ROM

with

In-Situ

Programming and Read-out protection

New ADC with a better accuracy and conversion
time

New configurable Clock, Reset and Supply
system

New power saving mode with real time base:
Active Halt

Beep capability on PF1

New interrupt source: Clock security system
(CSS) or Main clock controller (MCC)

ST72C334 I/O Configuration and Pinout

Same pinout as ST72E331

PA6 and PA7 are true open drain I/O ports
without pull-up (same as ST72E331)

PA3, PB3, PB4 and PF2 have no pull-up
configuration (all I/Os present on TQFP44)

PA5:4, PC3:2, PE7:4 and PF7:6 have high sink
capabilities (20mA on N-buffer, 2mA on P-buffer
and pull-up). On the ST72E331, all these pads
(except PA5:4) were 2mA push-pull pads
without high sink capabilities. PA4 and PA5
were 20mA true open drains.

New Memory Locations in ST72C334

20h: MISCR register becomes MISCR1 register
(naming change)

29h: new control/status register for the MCC
module

2Bh: new control/status register for the Clock,
Reset and Supply control. This register replaces
the WDGSR register keeping the WDOGF flag
compatibility.

40h: new MISCR2 register

ST72334J/N, ST72314J/N, ST72124J

5/148

2 INTRODUCTION

The ST72334J/N, ST72314J/N and ST72124J de-
vices are members of the ST7 microcontroller fam-
ily. They can be grouped as follows:

ST72334J/N devices are designed for mid-range

applications with Data EEPROM, ADC, SPI and
SCI interface capabilities.

ST72314J/N devices target the same range of

applications but without Data EEPROM.

ST72124J devices are for applications that do

not need Data EEPROM and the ADC peripher-
al.

All devices are based on a common industry-
standard 8-bit core, featuring an enhanced instruc-
tion set.

The

ST72C334J/N,

ST72C314J/N

and

ST72C124J

versions

feature

single-voltage

FLASH memory with byte-by-byte In-Situ Pro-
gramming (ISP) capability.

Under software control, all devices can be placed
in WAIT, SLOW, ACTIVE-HALT or HALT mode,
reducing power consumption when the application
is in idle or standby state.

The enhanced instruction set and addressing
modes of the ST7 offer both power and flexibility to
software developers, enabling the design of highly
efficient and compact application code. In addition
to standard 8-bit data management, all ST7 micro-
controllers feature true bit manipulation, 8x8 un-
signed multiplication and indirect addressing
modes.

For easy reference, all parametric data are located
in Section 15 on page 105.

Figure 1. General Block Diagram

8-BIT CORE

ALU

ADDRESS

AND

DATA

BUS

OSC1

ISPSEL

CONTROL

PROGRAM

(8K or 16K Bytes)

RESE T

PORT F

PF7,6,4,2:0

(6-BIT)

TIMER A

BEEP

PORT A

RAM

(384 or 512 Bytes)

PORT C

8-BIT ADC

DDA

SSA

PORT B

PB7:0

PORT E

PE7:0

SCI

TIMER B

PA7:0

PORT D

PD7:0

SPI

PC7:0

(8-BIT)

EEPROM

(256 Bytes)

WATCHDOG

MULTI OSC

LVD

OSC2

MEMORY

MCC/RTC

CLOCK FILTER

(8-BIT for N versions)
(5-BIT for J versions)

(6-BIT for N versions)
(2-BIT for J versions)

(8-BIT for N versions)
(6-BIT for J versions)

ST72334J/N, ST72314J/N, ST72124J

6/148

3 PIN DESCRIPTION

Figure 2. 64-Pin TQFP Package Pinout

(N versions)

DDA

SSA

DD_3

SS_3

MCO

PF0

BEEP

PF1

PF2

OCMP1_A

PF4

ICAP1_A

(HS)

PF6

EXTCLK_A

(HS)

PF7

AIN4

PD4

AIN5

PD5

AIN6

PD6

AIN7

PD7

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

17 18 19 20 21 22 23 24

29 30 31 32

25 26 27 28

ei2

ei3

ei0

ei1

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

(HS) PE4

(HS) PE5

(HS) PE6

(HS) PE7

PA1

PA0

PC7 / SS

PC6 / SCK / ISPCLK

PC5 / MOSI

PC4 / MISO / ISPDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B

PC0 / OCMP2_B

SS_0

DD_0

SS_1

DD_1

PA3

PA2

OSC1

OSC2

RESET

ISPSEL

PA7

(HS)

PA6

(HS)

PA5

(HS)

PA4

(HS)

PE1

RDI

PE0

TDO

(HS) 20mA high sink capability
ei

associated external interrupt vector

ST72334J/N, ST72314J/N, ST72124J

8/148

PIN DESCRIPTION (Cont'd)

Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts

(J versions)

MCO

PF0

BEEP

PF1

PF2

OCMP1_A

PF4

ICAP1_A

(HS)

PF6

EXTCLK_A

(HS)

PF7

DD_0

SS_0

AIN5

PD5

DDA

SSA

44 43 42 41 40 39 38 37 36 35 34

12 13 14 15 16 17 18 19 20 21 22

ei2

ei3

ei0

ei1

PB3

PB4

AIN0 / PD0

AIN1 / PD1

AIN2 / PD2

AIN3 / PD3

AIN4 / PD4

PE1 / RDI

PB0

PB1

PB2

PC6 / SCK / ISPC LK

PC5 / MOSI

PC4 / MISO / ISPDATA

PC3 (HS) / ICAP1_B

PC2 (HS) / ICAP2_B

PC1 / OCMP1_B

PC0 / OCMP2_B

SS_1

DD_1

PA3

PC7 / SS

RESET

ISPSEL

PA7

(HS)

PA6

(HS)

PA5

(HS)

PA4

(HS)

PE0

TDO

OSC1

OSC2

PB4

AIN0 / PD0

OCMP2_B / PC0

EXTCLK_A / (HS) PF7

ICAP1_A / (HS) PF6

OCMP1_A / PF4

PF2

BEEP / PF1

MCO / PF0

AIN5 / PD5

AIN4 / PD4

AIN3 / PD3

AIN2 / PD2

AIN1 / PD1

SSA

DDA

PB3

PB2

PA4 (HS)

PA5 (HS)

PA6 (HS)

PA7 (HS)

ISPSEL

RESET

PE0 / TDO

PE1 / RDI

PB0

PB1

OSC1

OSC2

EI3

ei0

ei2

ei1

MOSI / PC5

ISPDATA / MISO / PC4

ICAP1_B / (HS) PC3

ICAP2_B/ (HS) PC2

OCMP1_B / PC1

PC6 / SCK / ISPCLK

PC7 / SS

PA3

DD_1

SS_1

(HS) 20mA high sink capability
ei

associated external interrupt vector

ST72334J/N, ST72314J/N, ST72124J

9/148

PIN DESCRIPTION (Cont'd)

For external pin connection guidelines, refer to Section 15 "ELECTRICAL CHARACTERISTICS" on page
105.

Legend / Abbreviations for Table 1:

Type:

I = input, O = output, S = supply

Input level:

A = Dedicated analog input

In/Output level: C = CMOS 0.3V

/0.7V

= CMOS 0.3V

/0.7V

with input trigger

Output level:

HS = 20mA high sink (on N-buffer only)

Port and control configuration:

Input:

float = floating, wpu = weak pull-up, int = interrupt

, ana = analog

Output:

OD = open drain

, PP = push-pull

Refer to Section 11 "I/O PORTS" on page 37 for more details on the software configuration of the I/O
ports.

The RESET configuration of each pin is shown in bold. This configuration is valid as long as the device is
in reset state.

Table 1. Device Pin Description

Pin n

Pin Name

Type

Level

Port

Main

function

(after

reset)

Alternate function

TQFP64

SDIP56

QFP44

SDIP42

Input

Output

Input

Output

float

wpu

int

ana

1 49

PE4 (HS)

I/O C

Port E4

2 50

PE5 (HS)

I/O C

Port E5

3 51

PE6 (HS)

I/O C

Port E6

4 52

PE7 (HS)

I/O C

Port E7

5 53 2 39 PB0

I/O

ei2

Port B0

6 54 3 40 PB1

I/O

ei2

Port B1

7 55 4 41 PB2

I/O

ei2

Port B2

8 56 5 42 PB3

I/O

ei2

Port B3

PB4

I/O

ei3

Port B4

10 2

PB5

I/O

ei3

Port B5

11 3

PB6

I/O

ei3

Port B6

12 4

PB7

I/O

ei3

Port B7

13 5

PD0/AIN0

I/O

Port D0

ADC Analog Input 0

14 6

PD1/AIN1

I/O

Port D1

ADC Analog Input 1

15 7

PD2/AIN2

I/O

Port D2

ADC Analog Input 2

16 8 10 5

PD3/AIN3

I/O

Port D3

ADC Analog Input 3

17 9 11 6

PD4/AIN4

I/O

Port D4

ADC Analog Input 4

18 10 12 7

PD5/AIN5

I/O

Port D5

ADC Analog Input 5

19 11

PD6/AIN6

I/O

Port D6

ADC Analog Input 6

20 12

PD7/AIN7

I/O

Port D7

ADC Analog Input 7

21 13 13 8

DDA

Analog Power Supply Voltage

22 14 14 9

SSA

Analog Ground Voltage

DD_3

Digital Main Supply Voltage

ST72334J/N, ST72314J/N, ST72124J

10/148

SS_3

Digital Ground Voltage

25 15 15 10 PF0/MCO

I/O

ei1

Port F0

Main clock output (f

OSC

/2)

26 16 16 11 PF1/BEEP

I/O

ei1

Port F1

Beep signal output

27 17 17 12 PF2

I/O

ei1

Port F2

Not Connected

29 18 18 13 PF4/OCMP1_A

I/O

Port F4

Timer A Output Compare 1

Not Connected

31 19 19 14 PF6 (HS)/ICAP1_A

I/O C

Port F6

Timer A Input Capture 1

32 20 20 15 PF7 (HS)/EXTCLK_A I/O C

Port F7

Timer A External Clock Source

33 21 21

DD_0

Digital Main Supply Voltage

34 22 22

SS_0

Digital Ground Voltage

35 23 23 16 PC0/OCMP2_B

I/O

Port C0

Timer B Output Compare 2

36 24 24 17 PC1/OCMP1_B

I/O

Port C1

Timer B Output Compare 1

37 25 25 18 PC2 (HS)/ICAP2_B

I/O C

Port C2

Timer B Input Capture 2

38 26 26 19 PC3 (HS)/ICAP1_B

I/O C

Port C3

Timer B Input Capture 1

39 27 27 20 PC4/MISO

I/O

Port C4

SPI Master In / Slave Out Data

40 28 28 21 PC5/MOSI

I/O

Port C5

SPI Master Out / Slave In Data

41 29 29 22 PC6/SCK

I/O

Port C6

SPI Serial Clock

42 30 30 23 PC7/SS

I/O

Port C7

SPI Slave Select (active low)

43 31

PA0

I/O

ei0

Port A0

44 32

PA1

I/O

ei0

Port A1

45 33

PA2

I/O

ei0

Port A2

46 34 31 24 PA3

I/O

ei0

Port A3

47 35 32 25 V

DD_1

Digital Main Supply Voltage

48 36 33 26 V

SS_1

Digital Ground Voltage

49 37 34 27 PA4 (HS)

I/O C

Port A4

50 38 35 28 PA5 (HS)

I/O C

Port A5

51 39 36 29 PA6 (HS)

I/O C

Port A6

52 40 37 30 PA7 (HS)

I/O C

Port A7

53 41 38 31 ISPSEL

Must be tied low in user mode. In pro-
gramming mode when available, this pin
acts as In-Situ Programming mode se-
lection.

54 42 39 32 RESET

I/O

Top priority non maskable interrupt (ac-
tive low)

Not Connected

57 43 40 33 V

SS_3

Digital Ground Voltage

58 44 41 34 OSC2

Resonator oscillator inverter output or
capacitor input for RC oscillator

Pin n

Pin Name

Type

Level

Port

Main

function

(after

reset)

Alternate function

TQFP64

SDIP56

QFP44

SDIP42

Input

Output

Input

Output

float

wpu

int

ana

ST72334J/N, ST72314J/N, ST72124J

11/148

Notes:
1. In the interrupt input column, "ei

" defines the associated external interrupt vector. If the weak pull-up

column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input,
else the configuration is floating interrupt input.
2. In the open drain output column, "T" defines a true open drain I/O (P-Buffer and protection diode to V

are not implemented). See Section 11 "I/O PORTS" on page 37 and Section 15.8 "I/O PORT PIN CHAR-
ACTERISTICS" on page 125 for more details.

3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to
the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 6 and Section 15.5 "CLOCK AND TIM-
ING CHARACTERISTICS" on page 113 for more details.

59 45 42 35 OSC1

External clock input or Resonator oscilla-
tor inverter input or resistor input for RC
oscillator

60 46 43 36 V

DD_3

Digital Main Supply Voltage

61 47 44 37 PE0/TDO

I/O

Port E0

SCI Transmit Data Out

62 48 1 38 PE1/RDI

I/O

Port E1

SCI Receive Data In

Not Connected

Pin n

Pin Name

Type

Level

Port

Main

function

(after

reset)

Alternate function

TQFP64

SDIP56

QFP44

SDIP42

Input

Output

Input

Output

float

wpu

int

ana

ST72334J/N, ST72314J/N, ST72124J

12/148

4 REGISTER & MEMORY MAP

As shown in the Figure 5, the MCU is capable of
addressing 64K bytes of memories and I/O regis-
ters.

The available memory locations consist of 128
bytes of register locations, 384 or 512 bytes of
RAM, up to 256 bytes of data EEPROM and 4 or
8 Kbytes of user program memory. The RAM

space includes up to 256 bytes for the stack from
0100h to 01FFh.

The highest address bytes contain the user reset
and interrupt vectors.

IMPORTANT: Memory locations marked as "Re-
served" must never be accessed. Accessing a re-
seved area can have unpredicable effects on the
device.

Figure 5. Memory Map

0000h

Interrupt & Reset Vectors

HW Registers

027Fh

0080h

16-bit Addressing

RAM

007Fh

0200h / 0280h

0BFFh

Reserved

0080h

(see Table 2)

0C00h

FFDFh

FFE0h

FFFFh

(see Table 6 on page 32)

027Fh

C000h

Reserved

256 Bytes Data EEPROM

0CFFh

0D00h

BFFFh

00FFh

0100h

01FFh

0200h

8K Bytes

E000h

16K Bytes

Program

Short Addressing RAM

Zero page

0080h

00FFh

01FFh

384 Bytes RAM

512 Bytes RAM

Stack or

16-bit Addressing RAM

0100h

Memory

Program

Memory

8 KBytes

E000h

C000h

16 KBytes

FFFFh

(128 Bytes)

(256 Bytes)

Short Addressing RAM

Zero page

Stack or

16-bit Addressing RAM

(128 Bytes)

(256 Bytes)

ST72334J/N, ST72314J/N, ST72124J

13/148

REGISTER & MEMORY MAP (Cont'd)

Table 2. Hardware Register Map

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

0000h
0001h
0002h

Port A

PADR
PADDR
PAOR

Port A Data Register
Port A Data Direction Register
Port A Option Register

00h

00h
00h

R/W
R/W
R/W

0003h

Reserved Area (1 Byte)

0004h
0005h
0006h

Port C

PCDR
PCDDR
PCOR

Port C Data Register
Port C Data Direction Register
Port C Option Register

00h

00h
00h

R/W
R/W
R/W

0007h

Reserved Area (1 Byte)

0008h
0009h

000Ah

Port B

PBDR
PBDDR
PBOR

Port B Data Register
Port B Data Direction Register
Port B Option Register

00h

00h
00h

R/W
R/W

R/W

000Bh

Reserved Area (1 Byte)

000Ch
000Dh

000Eh

Port E

PEDR
PEDDR
PEOR

Port E Data Register
Port E Data Direction Register
Port E Option Register

00h

00h
00h

R/W
R/W
R/W

000Fh

Reserved Area (1 Byte)

0010h
0011h
0012h

Port D

PDDR
PDDDR
PDOR

Port D Data Register
Port D Data Direction Register
Port D Option Register

00h

00h
00h

R/W
R/W
R/W

0013h

Reserved Area (1 Byte)

0014h
0015h
0016h

Port F

PFDR
PFDDR
PFOR

Port F Data Register
Port F Data Direction Register
Port F Option Register

00h

00h
00h

R/W
R/W
R/W

0017h

001Fh

Reserved Area (9 Bytes)

0020h

MISCR1

Miscellaneous Register 1

00h

R/W

0021h
0022h
0023h

SPI

SPIDR
SPICR
SPISR

SPI Data I/O Register
SPI Control Register
SPI Status Register

xxh

0xh

00h

R/W
R/W
Read Only

0024h

0028h

Reserved Area (5 Bytes)

0029h

MCC

MCCSR

Main Clock Control / Status Register

01h

R/W

ST72334J/N, ST72314J/N, ST72124J

14/148

002Ah

WATCHDOG

WDGCR

Watchdog Control Register

7Fh

R/W

002Bh

CRSR

Clock, Reset, Supply Control / Status Register 000x 000x

R/W

002Ch

Data-EEPROM

EECSR

Data-EEPROM Control/Status Register

00h

R/W

002Dh

0030h

Reserved Area (4 Bytes)

0031h
0032h
0033h
0034h
0035h
0036h
0037h
0038h
0039h

003Ah
003Bh

003Ch
003Dh

003Eh
003Fh

TIMER A

TACR2
TACR1
TASR
TAIC1HR
TAIC1LR
TAOC1HR
TAOC1LR
TACHR
TACLR
TAACHR
TAACLR
TAIC2HR
TAIC2LR
TAOC2HR
TAOC2LR

Timer A Control Register 2
Timer A Control Register 1
Timer A Status Register
Timer A Input Capture 1 High Register
Timer A Input Capture 1 Low Register
Timer A Output Compare 1 High Register
Timer A Output Compare 1 Low Register
Timer A Counter High Register
Timer A Counter Low Register
Timer A Alternate Counter High Register
Timer A Alternate Counter Low Register
Timer A Input Capture 2 High Register
Timer A Input Capture 2 Low Register
Timer A Output Compare 2 High Register
Timer A Output Compare 2 Low Register

00h
00h

xxh
xxh
xxh

80h
00h

FFh

FCh

FFh

FCh

xxh
xxh

80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only

Read Only

R/W

0040h

MISCR2

Miscellaneous Register 2

00h

R/W

0041h
0042h
0043h
0044h
0045h
0046h
0047h
0048h
0049h

004Ah
004Bh

004Ch
004Dh

004Eh
004Fh

TIMER B

TBCR2
TBCR1
TBSR
TBIC1HR
TBIC1LR
TBOC1HR
TBOC1LR
TBCHR
TBCLR
TBACHR
TBACLR
TBIC2HR
TBIC2LR
TBOC2HR
TBOC2LR

Timer B Control Register 2
Timer B Control Register 1
Timer B Status Register
Timer B Input Capture 1 High Register
Timer B Input Capture 1 Low Register
Timer B Output Compare 1 High Register
Timer B Output Compare 1 Low Register
Timer B Counter High Register
Timer B Counter Low Register
Timer B Alternate Counter High Register
Timer B Alternate Counter Low Register
Timer B Input Capture 2 High Register
Timer B Input Capture 2 Low Register
Timer B Output Compare 2 High Register
Timer B Output Compare 2 Low Register

00h
00h

xxh
xxh
xxh

80h
00h

FFh

FCh

FFh

FCh

xxh
xxh

80h
00h

R/W
R/W
Read Only
Read Only
Read Only
R/W
R/W
Read Only
Read Only
Read Only
Read Only
Read Only
Read Only
R/W
R/W

0050h
0051h
0052h
0053h
0054h
0055h
0056h
0057h

SCI

SCISR
SCIDR
SCIBRR
SCICR1
SCICR2
SCIERPR

SCIETPR

SCI Status Register
SCI Data Register
SCI Baud Rate Register
SCI Control Register 1
SCI Control Register 2
SCI Extended Receive Prescaler Register
Reserved area
SCI Extended Transmit Prescaler Register

C0h

xxh

00xx xxxx

xxh

00h
00h

---

00h

Read Only
R/W
R/W
R/W
R/W
R/W

R/W

Address

Block

Register

Label

Register Name

Reset

Status

Remarks

ST72334J/N, ST72314J/N, ST72124J

16/148

5 FLASH PROGRAM MEMORY

5.1 INTRODUCTION

FLASH devices have a single voltage non-volatile
FLASH memory that may be programmed in-situ
(or plugged in a programming tool) on a byte-by-
byte basis.

5.2 MAIN FEATURES

Remote In-Situ Programming (ISP) mode

Up to 16 bytes programmed in the same cycle

MTP memory (Multiple Time Programmable)

Read-out memory protection against piracy

5.3 STRUCTURAL ORGANISATION

The FLASH program memory is organised in a
single 8-bit wide memory block which can be used
for storing both code and data constants.

The FLASH program memory is mapped in the up-
per part of the ST7 addressing space and includes
the reset and interrupt user vector area .

5.4 IN-SITU PROGRAMMING (ISP) MODE

The FLASH program memory can be programmed
using Remote ISP mode. This ISP mode allows
the contents of the ST7 program memory to be up-
dated using a standard ST7 programming tools af-
ter the device is mounted on the application board.
This feature can be implemented with a minimum
number of added components and board area im-
pact.

An example Remote ISP hardware interface to the
standard ST7 programming tool is described be-
low. For more details on ISP programming, refer to
the ST7 Programming Specification.

Remote ISP Overview

The Remote ISP mode is initiated by a specific se-
quence on the dedicated ISPSEL pin.

The Remote ISP is performed in three steps:

Selection of the RAM execution mode

Download of Remote ISP code in RAM

Execution of Remote ISP code in RAM to pro-

gram the user program into the FLASH

Remote ISP hardware configuration

In Remote ISP mode, the ST7 has to be supplied
with power (V

and V

) and a clock signal (os-

cillator and application crystal circuit for example).

This mode needs five signals (plus the V

signal

if necessary) to be connected to the programming
tool. This signals are:

RESET: device reset
V

: device ground power supply

ISPCLK: ISP output serial clock pin
ISPDATA: ISP input serial data pin
ISPSEL: Remote ISP mode selection. This pin

must be connected to V

on the application

board through a pull-down resistor.

If any of these pins are used for other purposes on
the application, a serial resistor has to be imple-
mented to avoid a conflict if the other device forces
the signal level.

Figure 6 shows a typical hardware interface to a
standard ST7 programming tool. For more details
on the pin locations, refer to the device pinout de-
scription.
Figure 6. Typical Remote ISP Interface

5.5 MEMORY READ-OUT PROTECTION

The read-out protection is enabled through an op-
tion bit.

For FLASH devices, when this option is selected,
the program and data stored in the FLASH memo-
ry are protected against read-out piracy (including
a re-write protection). When this protection option
is removed the entire FLASH program memory is
first automatically erased. However, the E

PROM

data memory (when available) can be protected
only with ROM devices.

ISPSEL

RESET

ISPCLK

ISPDATA

OSC1

OSC2

ST7

HE10 CONNECTOR TYPE

TO PROGRAMMING TOOL

10K

APPLICATION

47K

XTAL

ST72334J/N, ST72314J/N, ST72124J

18/148

DATA EEPROM (Cont'd)

6.3 MEMORY ACCESS

The Data EEPROM memory read/write access
modes are controlled by the LAT bit of the EEP-
ROM Control/Status register (EECSR). The flow-
chart in Figure 8 describes these different memory
access modes.

Read Operation (LAT=0)

The EEPROM can be read as a normal ROM loca-
tion when the LAT bit of the EECSR register is
cleared. In a read cycle, the byte to be accessed is
put on the data bus in less than 1 CPU clock cycle.
This means that reading data from EEPROM
takes the same time as reading data from
EPROM, but this memory cannot be used to exe-
cute machine code.

Write Operation (LAT=1)

To access the write mode, the LAT bit has to be
set by software (the PGM bit remains cleared).
When a write access to the EEPROM area occurs,
the value is latched inside the 16 data latches ac-
cording to its address.

When PGM bit is set by the software, all the previ-
ous bytes written in the data latches (up to 16) are
programmed in the EEPROM cells. The effective
high address (row) is determined by the last EEP-
ROM write sequence. To avoid wrong program-
ming, the user must take care that all the bytes
written between two programming sequences
have the same high address: only the four Least
Significant Bits of the address can change.

At the end of the programming cycle, the PGM and
LAT bits are cleared simultaneously, and an inter-
rupt is generated if the IE bit is set. The Data EEP-
ROM interrupt request is cleared by hardware
when the Data EEPROM interrupt vector is
fetched.

Note: Care should be taken during the program-
ming cycle. Writing to the same memory location
will over-program the memory (logical AND be-
tween the two write access data result) because
the data latches are only cleared at the end of the
programming cycle and by the falling edge of LAT
bit.
It is not possible to read the latched data.
This note is ilustrated by the Figure 9.

Figure 8. Data EEPROM Programming Flowchart

READ MODE

LAT=0

PGM=0

WRITE MODE

LAT=1

PGM=0

READ BYTES

IN EEPROM AREA

WRITE UP TO 16 BYTES

IN EEPROM AREA

(with the same 12 MSB of the address)

START PROGRAMMING CYCLE

LAT=1

PGM=1 (set by software)

LAT

INTERRUPT GENERATION

IF IE=1

CLEARED BY HARDWARE

ST72334J/N, ST72314J/N, ST72124J

19/148

DATA EEPROM (Cont'd)

6.4 POWER SAVING MODES

Wait mode

The DATA EEPROM can enter WAIT mode on ex-
ecution of the WFI instruction of the microcontrol-
ler. The DATA EEPROM will immediately enter
this mode if there is no programming in progress,
otherwise the DATA EEPROM will finish the cycle
and then enter WAIT mode.

Halt mode

The DATA EEPROM immediatly enters HALT
mode if the microcontroller executes the HALT in-
struction. Therefore the EEPROM will stop the
function in progress, and data may be corrupted.

6.5 ACCESS ERROR HANDLING

If a read access occurs while LAT=1, then the data
bus will not be driven.

If a write access occurs while LAT=0, then the
data on the bus will not be latched.

If a programming cycle is interrupted (by software/
RESET action), the memory data will not be guar-
anteed.

Figure 9. Data EEPROM Programming Cycle

LAT

ERASE CYCLE

WRITE CYCLE

PGM

PROG

READ OPERATION NOT POSSIBLE

WRITE OF

DATA LATCHES

READ OPERATION POSSIBLE

INTERNAL
PROGRAMMING
VOLTAGE

EEPROM INTERRUPT

ST72334J/N, ST72314J/N, ST72124J

20/148

DATA EEPROM (Cont'd)

6.6 REGISTER DESCRIPTION

CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:3 = Reserved, forced by hardware to 0.

Bit 2 = IE

Interrupt enable

This bit is set and cleared by software. It enables the
Data EEPROM interrupt capability when the PGM
bit is cleared by hardware. The interrupt request is
automatically cleared when the software enters the
interrupt routine.
0: Interrupt disabled
1: Interrupt enabled

Bit 1 = LAT

Latch Access Transfer

This bit is set by software. It is cleared by hard-
ware at the end of the programming cycle. It can
only be cleared by software if PGM bit is cleared.
0: Read mode
1: Write mode

Bit 0 = PGM

Programming control and status

This bit is set by software to begin the programming
cycle. At the end of the programming cycle, this bit
is cleared by hardware and an interrupt is generated
if the ITE bit is set.
0: Programming finished or not yet started
1: Programming cycle is in progress

Note: if the PGM bit is cleared during the program-
ming cycle, the memory data is not guaranteed

Table 3. DATA EEPROM Register Map and Reset Values

6.7 READ-OUT PROTECTION OPTION

The Data EEPROM can be optionally read-out
protected in ST72334 ROM devices (see option

list on page 145). ST72C334 Flash devices do not
have this protection option.

LAT

PGM

Address

(Hex.)

Register

Label

002Ch

EECSR

Reset Value

RWM

PGM

ST72334J/N, ST72314J/N, ST72124J

21/148

7 CENTRAL PROCESSING UNIT

7.1 INTRODUCTION

This CPU has a full 8-bit architecture and contains
six internal registers allowing efficient 8-bit data
manipulation.

7.2 MAIN FEATURES

63 basic instructions

Fast 8-bit by 8-bit multiply

17 main addressing modes

Two 8-bit index registers

16-bit stack pointer

Low power modes

Maskable hardware interrupts

Non-maskable software interrupt

7.3 CPU REGISTERS

The 6 CPU registers shown in Figure 10 are not
present in the memory mapping and are accessed
by specific instructions.

Accumulator (A)

The Accumulator is an 8-bit general purpose reg-
ister used to hold operands and the results of the
arithmetic and logic calculations and to manipulate
data.

Index Registers (X and Y)

In indexed addressing modes, these 8-bit registers
are used to create either effective addresses or
temporary storage areas for data manipulation.
(The Cross-Assembler generates a precede in-
struction (PRE) to indicate that the following in-
struction refers to the Y register.)

The Y register is not affected by the interrupt auto-
matic procedures (not pushed to and popped from
the stack).

Program Counter (PC)

The program counter is a 16-bit register containing
the address of the next instruction to be executed
by the CPU. It is made of two 8-bit registers PCL
(Program Counter Low which is the LSB) and PCH
(Program Counter High which is the MSB).

Figure 10. CPU Registers

ACCUMULATOR

X INDEX REGISTE R

Y INDEX REGISTE R

STACK POINTER

CONDITIO N CODE REGIST ER

PROGRAM COUNTER

1 1 H I

N Z

RESET VALUE = RESET VECTOR @ FFFEh-FFFFh

PCH

PCL

RESET VALUE = STACK HIGHER ADDRESS

RESET VALUE = 1

1 1 X 1 X X

RESET VALUE = XXh

X = Undefined Value

ST72334J/N, ST72314J/N, ST72124J

22/148

CPU REGISTERS (Cont'd)

CONDITION CODE REGISTER (CC)

Read/Write

Reset Value: 111x1xxx

The 8-bit Condition Code register contains the in-
terrupt mask and four flags representative of the
result of the instruction just executed. This register
can also be handled by the PUSH and POP in-
structions.

These bits can be individually tested and/or con-
trolled by specific instructions.

Bit 4 = H

Half carry.

This bit is set by hardware when a carry occurs be-
tween bits 3 and 4 of the ALU during an ADD or
ADC instruction. It is reset by hardware during the
same instructions.
0: No half carry has occurred.
1: A half carry has occurred.

This bit is tested using the JRH or JRNH instruc-
tion. The H bit is useful in BCD arithmetic subrou-
tines.

Bit 3 = I

Interrupt mask.

This bit is set by hardware when entering in inter-
rupt or by software to disable all interrupts except
the TRAP software interrupt. This bit is cleared by
software.
0: Interrupts are enabled.
1: Interrupts are disabled.

This bit is controlled by the RIM, SIM and IRET in-
structions and is tested by the JRM and JRNM in-
structions.

Note: Interrupts requested while I is set are
latched and can be processed when I is cleared.
By default an interrupt routine is not interruptable
because the I bit is set by hardware when you en-
ter it and reset by the IRET instruction at the end of
the interrupt routine. If the I bit is cleared by soft-
ware in the interrupt routine, pending interrupts are
serviced regardless of the priority level of the cur-
rent interrupt routine.

Bit 2 = N

Negative.

This bit is set and cleared by hardware. It is repre-
sentative of the result sign of the last arithmetic,
logical or data manipulation. It is a copy of the 7

bit of the result.
0: The result of the last operation is positive or null.
1: The result of the last operation is negative

(i.e. the most significant bit is a logic 1).

This bit is accessed by the JRMI and JRPL instruc-
tions.

Bit 1 = Z

Zero.

This bit is set and cleared by hardware. This bit in-
dicates that the result of the last arithmetic, logical
or data manipulation is zero.
0: The result of the last operation is different from

zero.

1: The result of the last operation is zero.

This bit is accessed by the JREQ and JRNE test
instructions.

Bit 0 = C

Carry/borrow.

This bit is set and cleared by hardware and soft-
ware. It indicates an overflow or an underflow has
occurred during the last arithmetic operation.
0: No overflow or underflow has occurred.
1: An overflow or underflow has occurred.

This bit is driven by the SCF and RCF instructions
and tested by the JRC and JRNC instructions. It is
also affected by the "bit test and branch", shift and
rotate instructions.

ST72334J/N, ST72314J/N, ST72124J

23/148

CENTRAL PROCESSING UNIT (Cont'd)

Stack Pointer (SP)

Read/Write

Reset Value: 01 FFh

The Stack Pointer is a 16-bit register which is al-
ways pointing to the next free location in the stack.
It is then decremented after data has been pushed
onto the stack and incremented before data is
popped from the stack (see Figure 11).

Since the stack is 256 bytes deep, the 8th most
significant bits are forced by hardware. Following
an MCU Reset, or after a Reset Stack Pointer in-
struction (RSP), the Stack Pointer contains its re-
set value (the SP7 to SP0 bits are set) which is the
stack higher address.

The least significant byte of the Stack Pointer
(called S) can be directly accessed by a LD in-
struction.

Note: When the lower limit is exceeded, the Stack
Pointer wraps around to the stack upper limit, with-
out indicating the stack overflow. The previously
stored information is then overwritten and there-
fore lost. The stack also wraps in case of an under-
flow.

The stack is used to save the return address dur-
ing a subroutine call and the CPU context during
an interrupt. The user may also directly manipulate
the stack by means of the PUSH and POP instruc-
tions. In the case of an interrupt, the PCL is stored
at the first location pointed to by the SP. Then the
other registers are stored in the next locations as
shown in Figure 11.

When an interrupt is received, the SP is decre-

mented and the context is pushed on the stack.

On return from interrupt, the SP is incremented

and the context is popped from the stack.

A subroutine call occupies two locations and an in-
terrupt five locations in the stack area.

Figure 11. Stack Manipulation Example

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

PCH

PCL

CALL

Subroutine

Interrupt

Event

PUSH Y

POP Y

IRET

RET

or RSP

@ 01FFh

@ 0100h

Stack Higher Address = 01FFh
Stack Lower Address = 0100h

ST72334J/N, ST72314J/N, ST72124J

24/148

8 SUPPLY, RESET AND CLOCK MANAGEMENT

The ST72334J/N, ST72314J/N and ST72124J mi-
crocontrollers include a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in Figure 12.

See Section 15 "ELECTRICAL CHARACTERIS-
TICS" on page 105 for more details.

Main Features

Supply Manager with main supply low voltage
detection (LVD)

Reset Sequence Manager (RSM)

Multi-Oscillator (MO)

4 Crystal/Ceramic resonator oscillators
1 External RC oscillator
1 Internal RC oscillator

Clock Security System (CSS)

Clock Filter
Backup Safe Oscillator

Figure 12. Clock, Reset and Supply Block Diagram

CRSR

CSS

WDG

OSC

CSS INTER RUPT

LVD

LOW VOLTAGE

DETECTO R

(LVD)

MULTI-

OSCILLATOR

(MO)

FROM

WATCH DOG

PERIP HERAL

OSC1

RESET

VDD

VSS

RESET SEQUEN CE

MANAGER

(RSM)

CLOCK

FILTE R

SAFE

OSC

CLOCK SECUR ITY SYSTE M

(CSS)

OSC2

MAIN CLOCK

CONTROLLER

ST72334J/N, ST72314J/N, ST72124J

25/148

8.1 LOW VOLTAGE DETECTOR (LVD)

To allow the integration of power management
features in the application, the Low Voltage Detec-
tor function (LVD) generates a static reset when
the V

supply voltage is below a V

IT-

reference

value. This means that it secures the power-up as
well as the power-down keeping the ST7 in reset.

The V

IT-

reference value for a voltage drop is lower

than the V

IT+

reference value for power-on in order

to avoid a parasitic reset when the MCU starts run-
ning and sinks current on the supply (hysteresis).

The LVD Reset circuitry generates a reset when
V

is below:

IT+

when V

is rising

IT-

when V

is falling

The LVD function is illustrated in the Figure 13.

Provided the minimum V

value (guaranteed for

the oscillator frequency) is above V

IT-

, the MCU

can only be in two modes:

under full software control
in static safe reset

In these conditions, secure operation is always en-
sured for the application without the need for ex-
ternal reset hardware.

During a Low Voltage Detector Reset, the RESET
pin is held low, thus permitting the MCU to reset
other devices.
Notes:
1. The LVD allows the device to be used without
any external RESET circuitry.
2. Three different reference levels are selectable
through the option byte according to the applica-
tion requirement.

LVD application note

Application software can detect a reset caused by
the LVD by reading the LVDRF bit in the CRSR
register.

This bit is set by hardware when a LVD reset is
generated and cleared by software (writing zero).

Figure 13. Low Voltage Detector vs Reset

IT+

RESET

IT-

hyst

ST72334J/N, ST72314J/N, ST72124J

27/148

RESET SEQUENCE MANAGER (Cont'd)

8.2.2 Asynchronous External RESET pin

The RESET pin is both an input and an open-drain
output with integrated R

weak pull-up resistor.

This pull-up has no fixed value but varies in ac-
cordance with the input voltage. It can be pulled
low by external circuitry to reset the device. See
electrical characteristics section for more details.

A RESET signal originating from an external
source must have a duration of at least t

h(RSTL)in

order to be recognized. This detection is asynchro-
nous and therefore the MCU can enter reset state
even in HALT mode.

The RESET pin is an asynchronous signal which
plays a major role in EMS performance. In a noisy
environment, it is recommended to follow the
guidelines mentioned in the electrical characteris-
tics section.

Two RESET sequences can be associated with
this RESET source: short or long external reset
pulse (see Figure 16).

Starting from the external RESET pulse recogni-
tion, the device RESET pin acts as an output that
is pulled low during at least t

w(RSTL)out

8.2.3 Internal Low Voltage Detection RESET

Two different RESET sequences caused by the in-
ternal LVD circuitry can be distinguished:

Power-On RESET

Voltage Drop RESET

The device RESET pin acts as an output that is
pulled low when V

IT+

(rising edge) or

IT-

(falling edge) as shown in Figure 16.

The LVD filters spikes on V

larger than t

g(VDD)

avoid parasitic resets.

8.2.4 Internal Watchdog RESET

The RESET sequence generated by a internal
Watchdog counter overflow is shown in Figure 16.

Starting from the Watchdog counter underflow, the
device RESET pin acts as an output that is pulled
low during at least t

w(RSTL)out

Figure 16. RESET Sequences

RUN

RESET PIN

EXTERNAL

WATCHDOG

DELAY

IT+

IT-

h(RSTL)in

w(RSTL)out

RUN

DELAY

h(RSTL)in

DELAY

WATCHDOG UNDERFLOW

w(RSTL)out

RUN

DELAY

RUN

RESET

RESET
SOURCE

SHORT EXT.

RESET

LVD

RESET

LONG EXT.

RESET

WATCHDOG

RESET

INTERNAL RESET (4096 T

CP U

)

FETCH VECTOR

ST72334J/N, ST72314J/N, ST72124J

28/148

8.3 MULTI-OSCILLATOR (MO)

The main clock of the ST7 can be generated by
four different source types coming from the multi-
oscillator block:

an external source

4 crystal or ceramic resonator oscillators

an external RC oscillator

an internal high frequency RC oscillator

Each oscillator is optimized for a given frequency
range in terms of consumption and is selectable
through the option byte. The associated hardware
configuration are shown in Table 4. Refer to the
electrical characteristics section for more details.

External Clock Source

In this external clock mode, a clock signal (square,
sinus or triangle) with ~50% duty cycle has to drive
the OSC1 pin while the OSC2 pin is tied to ground.

Crystal/Ceramic Oscillators

This family of oscillators has the advantage of pro-
ducing a very accurate rate on the main clock of
the ST7. The selection within a list of 4 oscillators
with different frequency ranges has to be done by
option byte in order to reduce consumption. In this
mode of the multi-oscillator, the resonator and the
load capacitors have to be placed as close as pos-
sible to the oscillator pins in order to minimize out-
put distortion and start-up stabilization time. The
loading capacitance values must be adjusted ac-
cording to the selected oscillator.

These oscillators are not stopped during the
RESET phase to avoid losing time in the oscillator
start-up phase.

External RC Oscillator

This oscillator allows a low cost solution for the
main clock of the ST7 using only an external resis-
tor and an external capacitor. The frequency of the
external RC oscillator (in the range of some MHz.)
is fixed by the resistor and the capacitor values.
Consequently in this MO mode, the accuracy of
the clock is directly linked to the accuracy of the
discrete components.

Internal RC Oscillator

The internal RC oscillator mode is based on the
same principle as the external RC oscillator includ-
ing the resistance and the capacitance of the de-
vice. This mode is the most cost effective one with
the drawback of a lower frequency accuracy. Its
frequency is in the range of several MHz.

In this mode, the two oscillator pins have to be tied
to ground.

Table 4. ST7 Clock Sources

Hardware Configur ation

External

Clock

Crystal/Ceramic

Resonators

External

Oscillator

Internal

Oscillator

OSC1

OSC2

EXTERNAL

ST7

SOURCE

OSC1

OSC2

LOAD

CAPACITORS

ST7

OSC1

OSC2

ST7

OSC1

OSC2

ST7

ST72334J/N, ST72314J/N, ST72124J

29/148

8.4 CLOCK SECURITY SYSTEM (CSS)

The Clock Security System (CSS) protects the
ST7 against main clock problems. To allow the in-
tegration of the security features in the applica-
tions, it is based on a clock filter control and an In-
ternal safe oscillator. The CSS can be enabled or
disabled by option byte.

8.4.1 Clock Filter Control

The clock filter is based on a clock frequency limi-
tation function.

This filter function is able to detect and filter high
frequency spikes on the ST7 main clock.

If the oscillator is not working properly (e.g. work-
ing at a harmonic frequency of the resonator), the
current active oscillator clock can be totally fil-
tered, and then no clock signal is available for the
ST7 from this oscillator anymore. If the original
clock source recovers, the filtering is stopped au-
tomatically and the oscillator supplies the ST7
clock.

8.4.2 Safe Oscillator Control

The safe oscillator of the CSS block is a low fre-
quency back-up clock source (see Figure 17).

If the clock signal disappears (due to a broken or
disconnected resonator...) during a safe oscillator
period, the safe oscillator delivers a low frequency
clock signal which allows the ST7 to perform some
rescue operations.

Automatically, the ST7 clock source switches back
from the safe oscillator if the original clock source
recovers.

Limitation detection

The automatic safe oscillator selection is notified
by hardware setting the CSSD bit of the CRSR
register. An interrupt can be generated if the CS-
SIE bit has been previously set.
These two bits are described in the CRSR register
description.

8.4.3 Low Power Modes

8.4.4 Interrupts

The CSS interrupt event generates an interrupt if
the corresponding Enable Control Bit (CSSIE) is
set and the interrupt mask in the CC register is re-
set (RIM instruction).

Figure 17. Clock Filter Function and Safe Oscillator Function

Mode

Description

WAIT

No effect on CSS. CSS interrupt cause the
device to exit from Wait mode.

HALT

The CRSR register is frozen. The CSS (in-
cluding the safe oscillator) is disabled until
HALT mode is exited. The previous CSS
configuration resumes when the MCU is
woken up by an interrupt with "exit from
HALT mode" capability or from the counter
reset value when the MCU is woken up by a
RESET.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

CSS event detection
(safe oscillator acti-
vated as main clock)

CSSD

CSSIE

Yes

OSC

CPU

OSC

CPU

SFOSC

SAFE

OSCILLATOR

FUNCTION

CLOCK

FILTER

FUNCTION

ST72334J/N, ST72314J/N, ST72124J

30/148

8.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION

Read/Write

Reset Value: 000x 000x (xxh)

Bit 7:5 = Reserved, always read as 0.

Bit 4 = LVDRF

LVD reset flag

This bit indicates that the last RESET was gener-
ated by the LVD block. It is set by hardware (LVD
reset) and cleared by software (writing zero). See
WDGRF flag description for more details. When
the LVD is disabled by option byte, the LVDRF bit
value is undefined.

Bit 3 = Reserved, always read as 0.

Bit 2 = CSSIE

Clock security syst

interrupt enable

This bit enables the interrupt when a disturbance
is detected by the clock security system (CSSD bit
set). It is set and cleared by software.
0: Clock security system interrupt disabled
1: Clock security system interrupt enabled
Refer to Table 6, "Interrupt Mapping," on page 32
for more details on the CSS interrupt vector. When
the CSS is disabled by option byte, the CSSIE bit
has no effect.

Bit 1 = CSSD

Clock security system detection

This bit indicates that the safe oscillator of the
clock security system block has been selected by
hardware due to a disturbance on the main clock
signal (f

OSC

). It is set by hardware and cleared by

reading the CRSR register when the original oscil-
lator recovers.
0: Safe oscillator is not active
1: Safe oscillator has been activated
When the CSS is disabled by option byte, the
CSSD bit value is forced to 0.

Bit 0 = WDGRF

Watchdog reset flag

This bit indicates that the last RESET was gener-
ated by the watchdog peripheral. It is set by hard-
ware (Watchdog RESET) and cleared by software
(writing zero) or an LVD RESET (to ensure a sta-
ble cleared state of the WDGRF flag when the
CPU starts).
Combined with the LVDRF flag information, the
flag description is given by the following table.

Application notes

The LVDRF flag is not cleared when another RE-
SET type occurs (external or watchdog), the
LVDRF flag remains set to keep trace of the origi-
nal failure.
In this case, a watchdog reset can be detected by
software while an external reset can not.

Table 5. Clock, Reset and Supply Register Map and Reset Values

LVD

CSS

WDG

RESET Sources

LVDRF

WDGRF

External RESET pin

Watchdog

LVD

Address

(Hex.)

Register

Label

002Bh

CRSR
Reset Value

LVDRF

CFIE

CSSD

WDGRF

ST72334J/N, ST72314J/N, ST72124J

31/148

9 INTERRUPTS

The ST7 core may be interrupted by one of two dif-
ferent methods: maskable hardware interrupts as
listed in the Interrupt Mapping Table and a non-
maskable software interrupt (TRAP). The Interrupt
processing flowchart is shown in Figure 18.
The maskable interrupts must be enabled clearing
the I bit in order to be serviced. However, disabled
interrupts may be latched and processed when
they are enabled (see external interrupts subsec-
tion).

When an interrupt has to be serviced:

Normal processing is suspended at the end of

the current instruction execution.

The PC, X, A and CC registers are saved onto

the stack.

The I bit of the CC register is set to prevent addi-

tional interrupts.

The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of
the interrupt service routine is fetched (refer to
the Interrupt Mapping Table for vector address-
es).

The interrupt service routine should finish with the
IRET instruction which causes the contents of the
saved registers to be recovered from the stack.

Note: As a consequence of the IRET instruction,
the I bit will be cleared and the main program will
resume.

Priority management

By default, a servicing interrupt cannot be inter-
rupted because the I bit is set by hardware enter-
ing in interrupt routine.

In the case when several interrupts are simultane-
ously pending, an hardware priority defines which
one will be serviced first (see the Interrupt Map-
ping Table).

Interrupts and Low power mode

All interrupts allow the processor to leave the
WAIT low power mode. Only external and specifi-
cally mentioned interrupts allow the processor to
leave the HALT low power mode (refer to the "Exit
from HALT" column in the Interrupt Mapping Ta-
ble).

9.1 NON MASKABLE SOFTWARE INTERRUPT

This interrupt is entered when the TRAP instruc-
tion is executed regardless of the state of the I bit.

It will be serviced according to the flowchart on
Figure 18.

9.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the
PC register if the corresponding external interrupt
occurred and if the I bit is cleared. These interrupts
allow the processor to leave the Halt low power
mode.

The external interrupt polarity is selected through
the miscellaneous register or interrupt register (if
available).

An external interrupt triggered on edge will be
latched and the interrupt request automatically
cleared upon entering the interrupt service routine.

If several input pins, connected to the same inter-
rupt vector, are configured as interrupts, their sig-
nals are logically ANDed before entering the edge/
level detection block.

Caution: The type of sensitivity defined in the Mis-
cellaneous or Interrupt register (if available) ap-
plies to the ei source. In case of an ANDed source
(as described on the I/O ports section), a low level
on an I/O pin configured as input with interrupt,
masks the interrupt request even in case of rising-
edge sensitivity.

9.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status
register are able to cause an interrupt when they
are active if both:

The I bit of the CC register is cleared.

The corresponding enable bit is set in the control

If any of these two conditions is false, the interrupt
is latched and thus remains pending.

Clearing an interrupt request is done by:

Writing "0" to the corresponding bit in the status

Access to the status register while the flag is set

followed by a read or write of an associated reg-
ister.

Note: the clearing sequence resets the internal
latch. A pending interrupt (i.e. waiting for being en-
abled) will therefore be lost if the clear sequence is
executed.

ST72334J/N, ST72314J/N, ST72124J

32/148

INTERRUPTS (Cont'd)

Figure 18. Interrupt Processing Flowchart

Table 6. Interrupt Mapping

Source

Block

Description

Register

Label

Priority

Order

Exit

from

HALT

Address

Vector

RESET

Reset

N/A

Highest

Priority

Lowest

Priority

yes

FFFE h-FFFFh

TRAP

Software Interrupt

FFFCh-FFFDh

Not used

FFFA h-FFFBh

MCC/RTC

CSS

Main Clock Controller Time Base Interrupt
or Clock Security System Interrupt

MCCSR

CRSR

yes

FFF8h-FFF9h

ei0

External Interrupt Port A3..0

N/A

FFF6h-FFF7h

ei1

External Interrupt Port F2..0

FFF4h-FFF5h

ei2

External Interrupt Port B3..0

FFF2h-FFF3h

ei3

External Interrupt Port B7..4

FFF0h-FFF1h

Not used

FFEEh-FFE Fh

SPI

SPI Peripheral Interrupts

SPISR

FFECh-FFE Dh

TIMER A

TIMER A Peripheral Interrupts

TASR

FFEAh-FFEBh

TIMER B

TIMER B Peripheral Interrupts

TBSR

FFE8h-FFE 9h

SCI

SCI Peripheral Interrupts

SCISR

FFE6h-FFE 7h

Data-EEPROM Data EEPROM Interrupt

EECSR

FFE4h-FFE 5h

Not used

FFE2h-FFE 3h

FFE0h-FFE 1h

I BIT SET?

IRET?

FROM RESET

LOAD PC FROM INTERRUPT VECTO R

STACK PC, X, A, CC

SET I BIT

FETCH NEXT INSTR UCTION

EXECU TE INSTRUCTION

THIS CLEARS I BIT BY DEFAULT

RESTORE PC, X, A, CC FROM STACK

INTE RRUPT

PENDING ?

ST72334J/N, ST72314J/N, ST72124J

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10 POWER SAVING MODES

10.1 INTRODUCTION

To give a large measure of flexibility to the applica-
tion in terms of power consumption, four main
power saving modes are implemented in the ST7
(see Figure 19): SLOW, WAIT (SLOW WAIT), AC-
TIVE HALT and HALT.

After a RESET the normal operating mode is se-
lected by default (RUN mode). This mode drives
the device (CPU and embedded peripherals) by
means of a master clock which is based on the
main oscillator frequency divided by 2 (f

CPU

From RUN mode, the different power saving
modes may be selected by setting the relevant
register bits or by calling the specific ST7 software
instruction whose action depends on the the oscil-
lator status.

Figure 19. Power Saving Mode Transitions

10.2 SLOW MODE

This mode has two targets:

To reduce power consumption by decreasing the

internal clock in the device,

To adapt the internal clock frequency (f

CPU

) to

the available supply voltage.

SLOW mode is controlled by three bits in the
MISCR1 register: the SMS bit which enables or
disables Slow mode and two CPx bits which select
the internal slow frequency (f

CPU

In this mode, the oscillator frequency can be divid-
ed by 4, 8, 16 or 32 instead of 2 in normal operat-
ing mode. The CPU and peripherals are clocked at
this lower frequency.

Note: SLOW-WAIT mode is activated when enter-
ring the WAIT mode while the device is already in
SLOW mode.

Figure 20. SLOW Mode Clock Transitions

POWER CONSUMPTION

WAIT

SLOW

RUN

ACTIVE HALT

High

Low

SLOW WAIT

HALT

SMS

CP1:0

CPU

NEW SLOW

NORMAL RUN MODE

MISCR1

FREQU ENCY

REQUEST

OSC

ST72334J/N, ST72314J/N, ST72124J

34/148

POWER SAVING MODES (Cont'd)

10.3 WAIT MODE

WAIT mode places the MCU in a low power con-
sumption mode by stopping the CPU.
This power saving mode is selected by calling the
`WFI' instruction.
All peripherals remain active. During WAIT mode,
the I bit of the CC register is cleared, to enable all
interrupts. All other registers and memory remain
unchanged. The MCU remains in WAIT mode until
an interrupt or RESET occurs, whereupon the Pro-
gram Counter branches to the starting address of
the interrupt or Reset service routine.
The MCU will remain in WAIT mode until a Reset
or an Interrupt occurs, causing it to wake up.

Refer to Figure 21.

Figure 21. WAIT Mode Flow-chart

Note:
1. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

WFI INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I BIT

ON
ON

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I BIT

OFF

CPU

OSCILLATOR
PERIPHERALS

I BIT

ON
ON

4096 CPU CLOCK CYCLE

DELAY

ST72334J/N, ST72314J/N, ST72124J

35/148

POWER SAVING MODES (Cont'd)

10.4 ACTIVE-HALT AND HALT MODES

ACTIVE-HALT and HALT modes are the two low-
est power consumption modes of the MCU. They
are both entered by executing the `HALT' instruc-
tion. The decision to enter either in ACTIVE-HALT
or HALT mode is given by the MCC/RTC interrupt
enable flag (OIE bit in MCCSR register).

10.4.1 ACTIVE-HALT MODE

ACTIVE-HALT mode is the lowest power con-
sumption mode of the MCU with a real time clock
available. It is entered by executing the `HALT' in-
struction when the OIE bit of the Main Clock Con-
troller Status register (MCCSR) is set (see Section
13.2 "MAIN CLOCK CONTROLLER WITH REAL
TIME CLOCK TIMER (MCC/RTC)" on page 50 for
more details on the MCCSR register).

The MCU can exit ACTIVE-HALT mode on recep-
tion of either an MCC/RTC interrupt, a specific in-
terrupt (see Table 6, "Interrupt Mapping," on
page 32) or a RESET. When exiting ACTIVE-
HALT mode by means of a RESET or an interrupt,
a 4096 CPU cycle delay occurs. After the start up
delay, the CPU resumes operation by servicing
the interrupt or by fetching the reset vector which
woke it up (see Figure 23).
When entering ACTIVE-HALT mode, the I bit in
the CC register is cleared to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.

In ACTIVE-HALT mode, only the main oscillator
and its associated counter (MCC/RTC) are run-
ning to keep a wake-up time base. All other periph-
erals are not clocked except those which get their
clock supply from another clock generator (such
as external or auxiliary oscillator).

The safeguard against staying locked in ACTIVE-
HALT mode is provided by the oscillator interrupt.

Note: As soon as the interrupt capability of one of
the oscillators is selected (MCCSR.OIE bit set),
entering ACTIVE-HALT mode while the Watchdog
is active does not generate a RESET.
This means that the device cannot spend more
than a defined delay in this power saving mode.

Figure 22. ACTIVE-HALT Timing Overview

Figure 23. ACTIVE-HALT Mode Flow-chart

Notes:
1. Peripheral clocked with an external clock source
can still be active.
2. Only the MCC/RTC interrupt and some specific
interrupts can exit the MCU from ACTIVE-HALT
mode (such as external interrupt). Refer to
Table 6, "Interrupt Mapping," on page 32 for more
details.
3. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

MCCSR

OIE bit

Power Saving Mode entered when HALT

instruction is executed

HALT mode

ACTIVE-HALT mode

HALT

RUN

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

ACTIVE

[MCCSR.OIE=1]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I BIT

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I BIT

OFF

CPU

OSCILLATOR
PERIPHERALS

I BITS

ON
ON

4096 CPU CLOCK CYCLE

DELAY

(MCCSR.OIE=1)

ST72334J/N, ST72314J/N, ST72124J

36/148

POWER SAVING MODES (Cont'd)

10.4.2 HALT MODE

The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
`HALT' instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see Section 13.2 "MAIN CLOCK CON-
TROLLER WITH REAL TIME CLOCK TIMER
(MCC/RTC)" on page 50 for more details on the
MCCSR register).

The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see Table 6, "Interrupt
Mapping," on page 32) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the
4096 CPU cycle delay is used to stabilize the os-
cillator. After the start up delay, the CPU resumes
operation by servicing the interrupt or by fetching
the reset vector which woke it up (see Figure 25).
When entering HALT mode, the I bit in the CC reg-
ister is forced to 0 to enable interrupts. Therefore,
if an interrupt is pending, the MCU wakes immedi-
ately.

In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).

The compatibility of Watchdog operation with
HALT mode is configured by the "WDGHALT" op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 17.1 on page 143 for more details).

Figure 24. HALT Timing Overview

Figure 25. HALT Mode Flow-chart

Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to Table 6, "Interrupt Mapping," on page 32 for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I bit of the CC register is
set during the interrupt routine and cleared when
the CC register is popped.

HALT

RUN

4096 CPU CYCLE

DELAY

RESET

INTERRUPT

HALT

INSTRUCTION

FETCH

VECTOR

[MCCSR.OIE=0]

HALT INSTRUCTION

RESET

INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I BIT

OFF
OFF

OFF

FETCH RESET VECTOR

OR SERVICE INTERRUPT

CPU

OSCILLATOR
PERIPHERALS

I BIT

OFF

CPU

OSCILLATOR
PERIPHERALS

I BITS

ON
ON

4096 CPU CLOCK CYCLE

DELAY

WATCHDOG

ENABLE

DISABLE

WDGHALT

WATCHDOG

RESET

(MCCSR.OIE=0)

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11 I/O PORTS

11.1 INTRODUCTION

The I/O ports offer different functional modes:
transfer of data through digital inputs and outputs

and for specific pins:
external interrupt generation
alternate signal input/output for the on-chip pe-

ripherals.

An I/O port contains up to 8 pins. Each pin can be
programmed independently as digital input (with or
without interrupt generation) or digital output.

11.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers:

Data Register (DR)

Data Direction Register (DDR)

and one optional register:

Option Register (OR)

Each I/O pin may be programmed using the corre-
sponding register bits in the DDR and OR regis-
ters: bit X corresponding to pin X of the port. The
same correspondence is used for the DR register.

The following description takes into account the
OR register, (for specific ports which do not pro-
vide this register refer to the I/O Port Implementa-
tion section). The generic I/O block diagram is
shown in Figure 26

11.2.1 Input Modes

The input configuration is selected by clearing the
corresponding DDR register bit.

In this case, reading the DR register returns the
digital value applied to the external I/O pin.

Different input modes can be selected by software
through the OR register.

Notes:
1. Writing the DR register modifies the latch value
but does not affect the pin status.
2. When switching from input to output mode, the
DR register has to be written first to drive the cor-
rect level on the pin as soon as the port is config-
ured as an output.

External interrupt function

When an I/O is configured as Input with Interrupt,
an event on this I/O can generate an external inter-
rupt request to the CPU.

Each pin can independently generate an interrupt
request. The interrupt sensitivity is independently

programmable using the sensitivity bits in the Mis-
cellaneous register.

Each external interrupt vector is linked to a dedi-
cated group of I/O port pins (see pinout description
and interrupt section). If several input pins are se-
lected simultaneously as interrupt source, these
are logically ANDed. For this reason if one of the
interrupt pins is tied low, it masks the other ones.

In case of a floating input with interrupt configura-
tion, special care must be taken when changing
the configuration (see Figure 27).

The external interrupts are hardware interrupts,
which means that the request latch (not accessible
directly by the application) is automatically cleared
when

the

corresponding

interrupt

vector

fetched. To clear an unwanted pending interrupt
by software, the sensitivity bits in the Miscellane-
ous register must be modified.

11.2.2 Output Modes

The output configuration is selected by setting the
corresponding DDR register bit. In this case, writ-
ing the DR register applies this digital value to the
I/O pin through the latch. Then reading the DR reg-
ister returns the previously stored value.

Two different output modes can be selected by
software through the OR register: Output push-pull
and open-drain.

DR register value and output pin status:

11.2.3 Alternate Functions

When an on-chip peripheral is configured to use a
pin, the alternate function is automatically select-
ed. This alternate function takes priority over the
standard I/O programming.

When the signal is coming from an on-chip periph-
eral, the I/O pin is automatically configured in out-
put mode (push-pull or open drain according to the
peripheral).

When the signal is going to an on-chip peripheral,
the I/O pin must be configured in input mode. In
this case, the pin state is also digitally readable by
addressing the DR register.

Note: Input pull-up configuration can cause unex-
pected value at the input of the alternate peripheral
input. When an on-chip peripheral use a pin as in-
put and output, this pin has to be configured in in-
put floating mode.

Push-pu ll

Open-drain

Vss

Floating

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I/O PORTS (Cont'd)

Figure 26. I/O Port General Block Diagram

Table 7. I/O Port Mode Options

Legend: NI - not implemented

Off - implemented not activated
On - implemented and activated

Note: The diode to V

is not implemented in the

true open drain pads. A local protection between
the pad and V

is implemented to protect the de-

vice against positive stress.

Configura tion Mode

Pull-Up

P-Buffer

Diodes

to V

Input

Floating with/without Interrupt

Off

Pull-up with/without Interrupt

Output

Push-pull

Off

Open Drain (logic level)

Off

True Open Drain

NI (see note)

DDR

DATA

BUS

PAD

ALTERNATE
ENABLE

ALTERNATE
OUTPUT

OR SEL

DDR SEL

DR SEL

PULL-UP
CONFIGURATION

P-BUFFER
(see table below)

N-BUFFER

PULL-UP
(see table below)

ANALOG

INPUT

If implemented

ALTERNATE

INPUT

DIODES
(see table below)

FROM
OTHER
BITS

EXTERNAL

SOURCE (ei

)

INTERRUPT

POLARITY

SELECTION

CMOS

SCHMITT
TRIGG ER

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I/O PORTS (Cont'd)

Table 8. I/O Port Configurations

Notes:
1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

2. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

Hardware Configu ration

INPUT

OPEN-DRAIN

OUTPUT

PUSH-PULL

OUTPUT

CONFIGURATION

PAD

EXTERNAL INTERR UPT

POLARITY

DATA BUS

PULL-UP

INTERRUPT

DR REGISTER ACCESS

FROM

OTHER

PINS

SOURCE (ei

)

SELECTI ON

REGISTE R

CONFIG URATION

ALTERNATE INPUT

NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS

ANALOG INPUT

PAD

DATA BUS

DR REGIST ER ACCESS

R/W

ALTERNATE

ENAB LE

OUTPUT

REGIST ER

NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS

PAD

DATA BUS

DR REGIST ER ACCESS

R/W

ALTERNATE

ENAB LE

OUTPUT

REGIST ER

NOT IMPLEMENTED IN
TRUE OPEN DRAIN
I/O PORTS

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I/O PORTS (Cont'd)

CAUTION: The alternate function must not be ac-
tivated as long as the pin is configured as input
with interrupt, in order to avoid generating spurious
interrupts.

Analog alternate function

When the pin is used as an ADC input, the I/O
must be configured as floating input. The analog
multiplexer (controlled by the ADC registers)
switches the analog voltage present on the select-
ed pin to the common analog rail which is connect-
ed to the ADC input.

It is recommended not to change the voltage level
or loading on any port pin while conversion is in
progress. Furthermore it is recommended not to
have clocking pins located close to a selected an-
alog pin.

WARNING: The analog input voltage level must
be within the limits stated in the absolute maxi-
mum ratings.

11.3 I/O PORT IMPLEMENTATION

The hardware implementation on each I/O port de-
pends on the settings in the DDR and OR registers
and specific feature of the I/O port such as ADC In-
put or true open drain.

Switching these I/O ports from one state to anoth-
er should be done in a sequence that prevents un-
wanted side effects. Recommended safe transi-
tions are illustrated in Figure 27 Other transitions
are potentially risky and should be avoided, since
they are likely to present unwanted side-effects
such as spurious interrupt generation.

Figure 27. Interrupt I/O Port State Transitions

The I/O port register configurations are summa-
rized as follows.

Standard Ports

PA5:4, PC7:0, PD7:0, PE7:4, PE1:0, PF7:6, PF4

Interrupt Ports

PA2:0, PB6:4, PB2:0, PF1:0 (with pull-up)

PA3, PB7, PB3, PF2 (without pull-up)

True Open Drain Ports

PA7:6

floating/pull-up

interrupt

INPUT

floating

(reset state)

INPUT

open-drain

OUTPUT

push-pull

OUTPUT

= DDR, OR

MODE

DDR

floating input

pull-up input

open drain output

push-pull output

MODE

DDR

floating input

pull-up interrupt input

open drain output

push-pull output

MODE

DDR

floating input

floating interrupt input

open drain output

push-pull output

MODE

DDR

floating input

open drain (high sink ports)

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I/O PORTS (Cont'd)

11.4 LOW POWER MODES

11.5 INTERRUPTS

The external interrupt event generates an interrupt
if the corresponding configuration is selected with
DDR and OR registers and the I-bit in the CC reg-
ister is reset (RIM instruction).

Table 9. Port Configuration

Mode

Description

WAIT

No effect on I/O ports. External interrupts
cause the device to exit from WAIT mode.

HALT

No effect on I/O ports. External interrupts
cause the device to exit from HALT mode.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

External interrupt on
selected external
event

DDRx

ORx

Yes

Port

Pin name

Input

Outpu t

OR = 0

OR = 1

OR = 0

OR = 1

High-Sink

Port A

PA7:6

floating

true open-drain

Yes

PA5:4

floating

pull-up

open drain

push-pull

PA3

floating

floating interrupt

open drain

push-pull

PA2:0

floating

pull-up interrupt

open drain

push-pull

Port B

PB7, PB3

floating

floating interrupt

open drain

push-pull

PB6:4, PB2:0

floating

pull-up interrupt

open drain

push-pull

Port C

PC7:4, PC1:0

floating

pull-up

open drain

push-pull

PC3:2

floating

pull-up

open drain

push-pull

Yes

Port D

PD7:0

floating

pull-up

open drain

push-pull

Port E

PE7:4

floating

pull-up

open drain

push-pull

Yes

PE1:0

floating

pull-up

open drain

push-pull

Port F

PF7:6

floating

pull-up

open drain

push-pull

Yes

PF4

floating

pull-up

open drain

push-pull

PF2

floating

floating interrupt

open drain

push-pull

PF1:0

floating

pull-up interrupt

open drain

push-pull

ST72334J/N, ST72314J/N, ST72124J

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I/O PORTS (Cont'd)

11.5.1 Register Description

DATA REGISTER (DR)

Port x Data Register
PxDR with x = A, B, C, D, E or F.

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = D[7:0]

Data register 8 bits.

The DR register has a specific behaviour accord-
ing to the selected input/output configuration. Writ-
ing the DR register is always taken into account
even if the pin is configured as an input; this allows
to always have the expected level on the pin when
toggling to output mode. Reading the DR register
returns either the DR register latch content (pin
configured as output) or the digital value applied to
the I/O pin (pin configured as input).

DATA DIRECTION REGISTER (DDR)

Port x Data Direction Register
PxDDR with x = A, B, C, D, E or F.

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = DD[7:0]

Data direction register 8 bits.

The DDR register gives the input/output direction
configuration of the pins. Each bits is set and
cleared by software.

0: Input mode
1: Output mode

OPTION REGISTER (OR)

Port x Option Register
PxOR with x = A, B, C, D, E or F.

Read/Write
Reset Value: 0000 0000 (00h)

Bit 7:0 = O[7:0]

Option register 8 bits.

For specific I/O pins, this register is not implement-
ed. In this case the DDR register is enough to se-
lect the I/O pin configuration.

The OR register allows to distinguish: in input
mode if the pull-up with interrupt capability or the
basic pull-up configuration is selected, in output
mode if the push-pull or open drain configuration is
selected.

Each bit is set and cleared by software.

Input mode:
0: floating input
1: pull-up input with or without interrupt

Output mode:
0: output open drain (with P-Buffer unactivated)
1: output push-pull

DD7

DD6

DD5

DD4

DD3

DD2

DD1

DD0

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12 MISCELLANEOUS REGISTERS

The miscellaneous registers allow control over
several different features such as the external in-
terrupts or the I/O alternate functions.

12.1 I/O PORT INTERRUPT SENSITIVITY

The external interrupt sensitivity is controlled by
the ISxx bits of the MISCR1 miscellaneous regis-
ter. This control allows to have two fully independ-
ent external interrupt source sensitivities.

Each external interrupt source can be generated
on four different events on the pin:

Falling edge

Rising edge

Falling and rising edge

Falling edge and low level

To guarantee correct functionality, the sensitivity
bits in the MISCR1 register must be modified only
when the I bit of the CC register is set to 1 (inter-
rupt masked). See I/O port register and Miscella-
neous register descriptions for more details on the
programming.

12.2 I/O PORT ALTERNATE FUNCTIONS

The MISCR registers manage four I/O port miscel-
laneous alternate functions:

Main clock signal (f

CPU

) output on PF0

A beep signal output on PF1 (with 3 selectable
audio frequencies)

SPI pin configuration:

SS pin internal control to use the PC7 I/O port

function while the SPI is active.

These functions are described in detail in the Sec-
tion 12 "MISCELLANEOUS REGISTERS" on
page 44.

Figure 28. Ext. Interrupt Sensitivity

ei2

INTERRU PT

SOURCE

IS10

IS11

MISCR1

SENSITIVITY

CONTROL

PB1
PB2

PB0

PB3

PB5
PB6

PB4

PB7

ei3

ei0

INTERRUPT

SOURCE

IS20

IS21

MISCR1

SENSITIVIT Y

CONTR OL

PA1
PA2

PA0

PA3

PF1
PF2

PF0

ei1

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MISCELLANEOUS REGISTERS (Cont'd)

12.3 REGISTERS DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = IS1[1:0]

ei2 and ei3 sensitivity

The interrupt sensitivity, defined using the IS1[1:0]
bits, is applied to the following external interrupts:
ei2 (port B3..0) and ei3 (port B7..4). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).

Bit 5 = MCO

Main clock out selection

This bit enables the MCO alternate function on the
I/O port. It is set and cleared by software.
0: MCO alternate function disabled

(I/O pin free for general-purpose I/O)

1: MCO alternate function enabled

OSC

/2 on I/O port)

Note: To reduce power consumption, the MCO
function is not active in ACTIVE-HALT mode.

Bit 4:3 = IS2[1:0]

ei0 and ei1 sensitivity

The interrupt sensitivity, defined using the IS2[1:0]
bits, is applied to the following external interrupts:-
ei0 (port A3..0) and ei1 (port F2..0). These 2 bits
can be written only when the I bit of the CC register
is set to 1 (interrupt disabled).

Bit 2:1 = CP[1:0]

CPU clock prescaler

These bits select the CPU clock prescaler which is
applied in the different slow modes. Their action is
conditioned by the setting of the SMS bit. These
two bits are set and cleared by software

Bit 0 = SMS

Slow mode select

This bit is set and cleared by software.
0: Normal mode. f

CPU

OSC

/ 2

1: Slow mode. f

CPU

is given by CP1, CP0

See low power consumption mode and MCC
chapters for more details.

IS11

IS10

MCO

IS21

IS20

CP1

CP0

SMS

External Interrupt Sensitivity

IS11 IS10

Falling edge & low level

Rising edge only

Falling edge only

Rising and falling edge

CPU

in SLOW mode

CP1 CP0

OSC

/ 4

OSC

/ 8

OSC

/ 16

OSC

/ 32

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MISCELLANEOUS REGISTERS (Cont'd)

MISCELLANEOUS REGISTER 2 (MISCR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7:6 = Reserved

Must always be cleared

Bit 5:4 = BC[1:0]

Beep control

These 2 bits select the PF1 pin beep capability.

The beep output signal is available in ACTIVE-
HALT mode but has to be disabled to reduce the
consumption.

Bit 3:2 = Reserved

Must always be cleared

Bit 1 = SSM

SS mode selection

It is set and cleared by software.
0: Normal mode - SS uses information coming
from the SS pin of the SPI.
1: I/O mode, the SPI uses the information stored
into bit SSI.

Bit 0 = SSI

SS internal mode

This bit replaces pin SS of the SPI when bit SSM is
set to 1. (see SPI description). It is set and cleared
by software.

Table 11. Miscellaneous Register Map and Reset Values

BC1

BC0

SSM

SSI

Beep mode with f

OSC

=16MHz

BC1 BC0

Off

~2-KHz

Output

Beep signal

~50% duty cycle

~1-KHz

~500-Hz

Address

(Hex.)

Register

Label

0020h

MISCR1
Reset Value

IS11

IS10

MCO

IS21

IS20

CP1

CP0

SMS

0040h

MISCR2
Reset Value

BC1

BC0

SSM

SSI

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13 ON-CHIP PERIPHERALS

13.1 WATCHDOG TIMER (WDG)

13.1.1 Introduction

The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter's contents before the T6 bit be-
comes cleared.

13.1.2 Main Features

Programmable timer (64 increments of 12288
CPU cycles)

Programmable reset

Reset (if watchdog activated) after a HALT
instruction or when the T6 bit reaches zero

Hardware Watchdog selectable by option byte

Watchdog Reset indicated by status flag (in
versions with Safe Reset option only)

13.1.3 Functional Description

The counter value stored in the CR register (bits
T[6:0]), is decremented every 12,288 machine cy-
cles, and the length of the timeout period can be
programmed by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.

Figure 29. Watchdog Block Diagram

RESET

WDGA

7-BIT DOWNCOUNTER

CPU

CLOCK DIVIDER

WATCHDOG CONTROL REGISTER (CR)

12288

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WATCHDOG TIMER (Cont'd)

The application program must write in the CR reg-
ister at regular intervals during normal operation to
prevent an MCU reset. The value to be stored in
the CR register must be between FFh and C0h
(see Table 12 .Watchdog Timing (fCPU = 8 MHz)):

The WDGA bit is set (watchdog enabled)

The T6 bit is set to prevent generating an imme-

diate reset

The T[5:0] bits contain the number of increments

which represents the time delay before the
watchdog produces a reset.

Table 12.Watchdog Timing (f

CPU

= 8 MHz)

Notes: Following a reset, the watchdog is disa-
bled. Once activated it cannot be disabled, except
by a reset.

The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction
will generate a Reset.

13.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte,
the watchdog is always active and the WDGA bit in
the CR is not used.

Refer to the device-specific Option Byte descrip-
tion.

13.1.5 Low Power Modes

13.1.6 Interrupts

None.

13.1.7 Register Description

CONTROL REGISTER (CR)

Read/Write

Reset Value: 0111 1111 (7Fh)

Bit 7 = WDGA

Activation bit.

This bit is set by software and only cleared by
hardware after a reset. When WDGA = 1, the
watchdog can generate a reset.
0: Watchdog disabled
1: Watchdog enabled

Note: This bit is not used if the hardware watch-
dog option is enabled by option byte.

Bit 6:0 = T[6:0]

7-bit timer (MSB to LSB).

These bits contain the decremented value. A reset
is produced when it rolls over from 40h to 3Fh (T6
becomes cleared).

STATUS REGISTER (SR)

Read/Write

Reset Value*: 0000 0000 (00h)

Bit 0 = WDOGF

Watchdog flag.

This bit is set by a watchdog reset and cleared by
software or a power on/off reset. This bit is useful
for distinguishing power/on off or external reset
and watchdog reset.
0: No Watchdog reset occurred
1: Watchdog reset occurred

* Only by software and power on/off reset

Note: This register is not used in versions without
LVD Reset.

CR Register

initial value

WDG timeout period

(ms)

Max

FFh

98.304

Min

C0h

1.536

Mode

Description

WAIT

No effect on Watchdog.

HALT

Immediate reset generation as soon as
the HALT instruction is executed if the
Watchdog is activated (WDGA bit is
set).

WDGA

WDOGF

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13.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)

The Main Clock Controller consists of three differ-
ent functions:

a programmable CPU clock prescaler

a clock-out signal to supply external devices

a real time clock timer with interrupt capability

Each function can be used independently and si-
multaneously.

13.2.1 Programmable CPU clock prescaler

The programmable CPU clock prescaler supplies
the clock for the ST7 CPU and its internal periph-
erals. It manages SLOW power saving mode (See
Section 10.2 "SLOW MODE" on page 33 for more
details).

The prescaler selects the f

CPU

main clock frequen-

cy and is controlled by three bits in the MISCR1
register: CP[1:0] and SMS.

CAUTION: The prescaler does not act on the CAN
peripheral clock source. This peripheral is always
supplied by the f

OSC

/2 clock source.

13.2.2 Clock-out capability

The clock-out capability is an alternate function of
an I/O port pin that outputs a f

OSC

/2 clock to drive

external devices. It is controlled by the MCO bit in
the MISCR1 register.
CAUTION: When selected, the clock out pin sus-
pends the clock during ACTIVE-HALT mode.

13.2.3 Real time clock timer (RTC)

The counter of the real time clock timer allows an
interrupt to be generated based on an accurate
real time clock. Four different time bases depend-
ing directly on f

OSC

are available. The whole func-

tionality is controlled by four bits of the MCCSR
register: TB[1:0], OIE and OIF.

When the RTC interrupt is enabled (OIE bit set),
the ST7 enters ACTIVE-HALT mode when the
HALT instruction is executed. See Section 10.4
"ACTIVE-HALT AND HALT MODES" on page 35
for more details.

Figure 30. Main Clock Controller (MCC/RTC) Block Diagram

DIV2, 4, 8, 16

MCC/RTC INTERRUPT

DIV 2

SMS

CP1 CP0

TB1 TB0 OIE OIF

CPU CLOCK

MISCR1

RTC

COUNTER

TO CPU AND

PERIPHERALS

OSC

CPU

MCO

PORT

FUNCTION

ALTERNATE

MCO

MCCSR

OSC

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MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (Cont'd)

MISCELLANEOUS REGISTER 1 (MISCR1)

See Section 12 on page 44.

MAIN CLOCK CONTROL/STATUS REGISTER
(MCCSR)

Read/Write

Reset Value: 0000 0001 (01h)

Bit 7:4 = Reserved, always read as 0.

Bit 3:2 = TB[1:0]

Time base control

These bits select the programmable divider time
base. They are set and cleared by software.

A modification of the time base is taken into ac-
count at the end of the current period (previously
set) to avoid unwanted time shift. This allows to
use this time base as a real time clock.

Bit 1 = OIE

Oscillator interrupt enable

This bit set and cleared by software.
0: Oscillator interrupt disabled
1: Oscillator interrupt enabled
This interrupt allows to exit from ACTIVE-HALT
mode.
When this bit is set, calling the ST7 software HALT
instruction enters the ACTIVE-HALT power saving
mode

Bit 0 = OIF

Oscillator interrupt flag

This bit is set by hardware and cleared by software
reading the CSR register. It indicates when set
that the main oscillator has measured the selected
elapsed time (TB1:0).
0: Timeout not reached
1: Timeout reached

CAUTION: The BRES and BSET instructions
must not be used on the MCCSR register to avoid
unintentionally clearing the OIF bit.

13.2.4 Low Power Modes

13.2.5 Interrupts

The MCC/RTC interrupt event generates an inter-
rupt if the OIE bit of the MCCSR register is set and
the interrupt mask in the CC register is not active
(RIM instruction).

Note:

1. The MCC/RTC interrupt allows to exit from AC-
TIVE-HALT mode, not from HALT mode.

Table 14. MCC Register Map and Reset Values

TB1

TB0

OIE

OIF

Counter

Prescaler

Time Base

TB1

TB0

OSC

=8MHz

OSC

=16MHz

32000

4ms

2ms

64000

8ms

4ms

160000

20ms

10ms

400000

50ms

25ms

Mode

Descriptio n

WAIT

No effect on MCC/RTC peripheral.
MCC/RTC interrupt cause the device to exit
from WAIT mode.

ACTIVE-
HALT

No effect on MCC/RTC counter (OIE bit is
set), the registers are frozen.
MCC/RTC interrupt cause the device to exit
from ACTIVE-HALT mode.

HALT

MCC/RTC counter and registers are frozen.
MCC/RTC operation resumes when the
MCU is woken up by an interrupt with "exit
from HALT" capability.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Time base overflow
event

OIF

OIE

Yes

Address

(Hex.)

Register

Label

0029h

MCCSR
Reset Value

TB1

TB0

OIE

OIF

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13.3 16-BIT TIMER

13.3.1 Introduction

The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.

It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (

input capture) or generation of up to two out-

put waveforms (

output compare and PWM).

Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.

Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.

This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).

13.3.2 Main Features

Programmable prescaler: f

CPU

divided by 2, 4 or 8.

Overflow status flag and maskable interrupt

External clock input (must be at least 4 times
slower than the CPU clock speed) with the choice
of active edge

Output compare functions with

2 dedicated 16-bit registers

2 dedicated programmable signals

2 dedicated status flags

1 dedicated maskable interrupt

Input capture functions with

2 dedicated 16-bit registers

2 dedicated active edge selection signals

2 dedicated status flags

1 dedicated maskable interrupt

Pulse width modulation mode (PWM)

One pulse mode

5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*

The Block Diagram is shown in Figure 31.

*Note: Some timer pins may not available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be `1'.

13.3.3 Functional Description

13.3.3.1 Counter

The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.

Counter Register (CR):

Counter High Register (CHR) is the most sig-

nificant byte (MS Byte).

Counter Low Register (CLR) is the least sig-

nificant byte (LS Byte).

Alternate Counter Register (ACR)

Alternate Counter High Register (ACHR) is the

most significant byte (MS Byte).

Alternate Counter Low Register (ACLR) is the

least significant byte (LS Byte).

These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).

Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.

The timer clock depends on the clock control bits
of the CR2 register, as illustrated in Table 15 Clock
Control Bits. The value in the counter register re-
peats every 131.072, 262.144 or 524.288 CPU
clock cycles depending on the CC[1:0] bits.
The timer frequency can be f

CPU

/2, f

CPU

/4, f

CPU

or an external frequency.

ST72334J/N, ST72314J/N, ST72124J

54/148

16-BIT TIMER (Cont'd)

16-bit read sequence: (from either the Counter
Register or the Alternate Counter Register).

The user must read the MS Byte first, then the LS
Byte value is buffered automatically.

This buffered value remains unchanged until the
16-bit read sequence is completed, even if the
user reads the MS Byte several times.

After a complete reading sequence, if only the
CLR register or ACLR register are read, they re-
turn the LS Byte of the count value at the time of
the read.

Whatever the timer mode used (input capture, out-
put compare, one pulse mode or PWM mode) an
overflow occurs when the counter rolls over from
FFFFh to 0000h then:

The TOF bit of the SR register is set.

A timer interrupt is generated if:

TOIE bit of the CR1 register is set and

I bit of the CC register is cleared.

If one of these conditions is false, the interrupt re-
mains pending to be issued as soon as they are
both true.

Clearing the overflow interrupt request is done in
two steps:

1. Reading the SR register while the TOF bit is set.
2. An access (read or write) to the CLR register.

Notes: The TOF bit is not cleared by accesses to
ACLR register. The advantage of accessing the
ACLR register rather than the CLR register is that
it allows simultaneous use of the overflow function
and reading the free running counter at random
times (for example, to measure elapsed time) with-
out the risk of clearing the TOF bit erroneously.

The timer is not affected by WAIT mode.

In HALT mode, the counter stops counting until the
mode is exited. Counting then resumes from the
previous count (MCU awakened by an interrupt) or
from the reset count (MCU awakened by a Reset).

13.3.3.2 External Clock

The external clock (where available) is selected if
CC0=1 and CC1=1 in CR2 register.

The status of the EXEDG bit in the CR2 register
determines the type of level transition on the exter-
nal clock pin EXTCLK that will trigger the free run-
ning counter.

The counter is synchronised with the falling edge
of the internal CPU clock.

A minimum of four falling edges of the CPU clock
must occur between two consecutive active edges
of the external clock; thus the external clock fre-
quency must be less than a quarter of the CPU
clock frequency.

is buffered

Read

At t0

Read

Returns the buffered

LS Byte value at t0

At t0 +

Other

instructions

Beginning of the sequence

Sequence completed

LS Byte

MS Byte

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16-BIT TIMER (Cont'd)

13.3.3.3 Input Capture

In this section, the index,

i, may be 1 or 2 because

there are 2 input capture functions in the 16-bit
timer.

The two input capture 16-bit registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition detected by the
ICAP

i pin (see figure 5).

iR register is a read-only register.

The active transition is software programmable
through the IEDG

i bit of Control Registers (CRi).

Timing resolution is one count of the free running
counter: (

CPU

CC[1:0]).

Procedure:

To use the input capture function select the follow-
ing in the CR2 register:

Select the timer clock (CC[1:0]) (see Table 15

Clock Control Bits).

Select the edge of the active transition on the

ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input).

And select the following in the CR1 register:

Set the ICIE bit to generate an interrupt after an

input capture coming from either the ICAP1 pin
or the ICAP2 pin

Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input).

When an input capture occurs:

ICF

i bit is set.

The IC

iR register contains the value of the free

running counter on the active transition on the
ICAP

i pin (see Figure 36).

A timer interrupt is generated if the ICIE bit is set

and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.

Clearing the Input Capture interrupt request (i.e.
clearing the ICF

i bit) is done in two steps:

1. Reading the SR register while the ICF

i bit is set.

2. An access (read or write) to the IC

iLR register.

Notes:

1. After reading the IC

iHR register, transfer of

input capture data is inhibited and ICF

i will

never be set until the IC

iLR register is also

read.

2. The IC

iR register contains the free running

counter value which corresponds to the most
recent input capture.

3. The 2 input capture functions can be used

together even if the timer also uses the 2 output
compare functions.

4. In One pulse Mode and PWM mode only the

input capture 2 can be used.

5. The alternate inputs (ICAP1 & ICAP2) are

always directly connected to the timer. So any
transitions on these pins activate the input cap-
ture function.
Moreover if one of the ICAP

i pin is configured

as an input and the second one as an output,
an interrupt can be generated if the user toggle
the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion

i is disabled by reading the ICiHR (see note

1).

6. The TOF bit can be used with interrupt in order

to measure event that go beyond the timer
range (FFFFh).

MS Byte

LS Byte

ICiR

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16-BIT TIMER (Cont'd)

13.3.3.4 Output Compare

In this section, the index,

i, may be 1 or 2 because

there are 2 output compare functions in the 16-bit
timer.

This function can be used to control an output
waveform or indicate when a period of time has
elapsed.

When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:

Assigns pins with a programmable value if the

OCIE bit is set

Sets a flag in the status register

Generates an interrupt if enabled

Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.

These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC

R value to 8000h.

Timing resolution is one count of the free running
counter: (

CPU/

CC[1:0]

Procedure:

To use the output compare function, select the fol-
lowing in the CR2 register:

Set the OC

iE bit if an output is needed then the

OCMP

i pin is dedicated to the output compare i

signal.

Select the timer clock (CC[1:0]) (see Table 15

Clock Control Bits).

And select the following in the CR1 register:

Select the OLVL

i bit to applied to the OCMPi pins

after the match occurs.

Set the OCIE bit to generate an interrupt if it is

needed.

When a match is found between OCRi register
and CR register:

OCF

i bit is set.

The OCMP

i pin takes OLVLi bit value (OCMPi

pin latch is forced low during reset).

A timer interrupt is generated if the OCIE bit is

set in the CR2 register and the I bit is cleared in
the CC register (CC).

The OC

R register value required for a specific tim-

ing application can be calculated using the follow-
ing formula:

Where:

= Output compare period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 de-

pending on CC[1:0] bits, see Table 15
Clock Control Bits)

If the timer clock is an external clock, the formula
is:

Where:

= Output compare period (in seconds)

EXT

= External timer clock frequency (in hertz)

Clearing the output compare interrupt request (i.e.
clearing the OCF

i bit) is done by:

1. Reading the SR register while the OCF

i bit is

set.

2. An access (read or write) to the OC

iLR register.

The following procedure is recommended to pre-
vent the OCF

i bit from being set between the time

it is read and the write to the OC

R register:

Write to the OC

iHR register (further compares

are inhibited).

Read the SR register (first step of the clearance

of the OCF

i bit, which may be already set).

Write to the OC

iLR register (enables the output

compare function and clears the OCF

i bit).

MS Byte

LS Byte

iR =

CPU

PRESC

iR =

EXT

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16-BIT TIMER (Cont'd)

Notes:

1. After a processor write cycle to the OC

iHR reg-

ister, the output compare function is inhibited
until the OC

iLR register is also written.

2. If the OC

iE bit is not set, the OCMPi pin is a

general I/O port and the OLVL

i bit will not

appear when a match is found but an interrupt
could be generated if the OCIE bit is set.

3. When the timer clock is f

CPU

/2, OCF

i and

OCMP

i are set while the counter value equals

the OC

iR register value (see Figure 38 on page

60). This behaviour is the same in OPM or
PWM mode.
When the timer clock is f

CPU

/4, f

CPU

/8 or in

external clock mode, OCF

i and OCMPi are set

while the counter value equals the OC

iR regis-

ter value plus 1 (see Figure 39 on page 60).

4. The output compare functions can be used both

for generating external events on the OCMP

pins even if the input capture mode is also
used.

5. The value in the 16-bit OC

R register and the

OLV

i bit should be changed after each suc-

cessful comparison in order to control an output
waveform or establish a new elapsed timeout.

Forced Compare Output capability

When the FOLV

i bit is set by software, the OLVLi

bit is copied to the OCMP

i pin. The OLVi bit has to

be toggled in order to toggle the OCMP

i pin when

it is enabled (OC

iE bit=1). The OCFi bit is then not

set by hardware, and thus no interrupt request is
generated.

FOLVL

i bits have no effect in both one pulse mode

and PWM mode.

Figure 37. Output Compare Block Diagram

OUTPUT COMPARE

16-bit

CIRCUIT

OC1R Register

16 BIT FREE RUNNING

COUNTER

OC1E

CC0

CC1

OC2E

OLVL1

OLVL2

OCIE

(Control Register 1) CR1

(Control Register 2) CR2

OCF2

OCF1

(Status Register) SR

16-bit

OCMP1

OCMP2

Latch

OC2R Register

FOLV2 FOLV1

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16-BIT TIMER (Cont'd)

13.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a
pulse when an external event occurs. This mode is
selected via the OPM bit in the CR2 register.

The one pulse mode uses the Input Capture1
function and the Output Compare1 function.

Procedure:

To use one pulse mode:

1. Load the OC1R register with the value corre-

sponding to the length of the pulse (see the for-
mula in the opposite column).

2. Select the following in the CR1 register:

Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after the pulse.

Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin during the pulse.

Select the edge of the active transition on the

ICAP1 pin with the IEDG1 bit (the ICAP1 pin
must be configured as floating input).

3. Select the following in the CR2 register:

Set the OC1E bit, the OCMP1 pin is then ded-

icated to the Output Compare 1 function.

Set the OPM bit.

Select the timer clock CC[1:0] (see Table 15

Clock Control Bits).

Then, on a valid event on the ICAP1 pin, the coun-
ter is initialized to FFFCh and OLVL2 bit is loaded
on the OCMP1 pin, the ICF1 bit is set and the val-
ue FFFDh is loaded in the IC1R register.

Because the ICF1 bit is set when an active edge
occurs, an interrupt can be generated if the ICIE
bit is set.

Clearing the Input Capture interrupt request (i.e.
clearing the ICF

i bit) is done in two steps:

1. Reading the SR register while the ICF

i bit is set.

2. An access (read or write) to the IC

iLR register.

The OC1R register value required for a specific
timing application can be calculated using the fol-
lowing formula:

Where:
t

= Pulse period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on the CC[1:0] bits, see Table 15
Clock Control Bits)

If the timer clock is an external clock the formula is:

Where:

= Pulse period (in seconds)

EXT

= External timer clock frequency (in hertz)

When the value of the counter is equal to the value
of the contents of the OC1R register, the OLVL1
bit is output on the OCMP1 pin, (See Figure 40).

Notes:

1. The OCF1 bit cannot be set by hardware in one

pulse mode but the OCF2 bit can generate an
Output Compare interrupt.

2. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.

3. If OLVL1=OLVL2 a continuous signal will be

seen on the OCMP1 pin.

4. The ICAP1 pin can not be used to perform input

capture. The ICAP2 pin can be used to perform
input capture (ICF2 can be set and IC2R can be
loaded) but the user must take care that the
counter is reset each time a valid edge occurs
on the ICAP1 pin and ICF1 can also generates
interrupt if ICIE is set.

5. When one pulse mode is used OC1R is dedi-

cated to this mode. Nevertheless OC2R and
OCF2 can be used to indicate a period of time
has been elapsed but cannot generate an out-
put waveform because the level OLVL2 is dedi-
cated to the one pulse mode.

event occurs

Counter
= OC1R

OCMP1 = OLVL1

When

on ICAP1

One pulse mode cycle

OCMP1 = OLVL2

Counter is reset

to FFFCh

ICF1 bit is set

iR Value =

CPU

PRESC

- 5

iR =

EXT

-5

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16-BIT TIMER (Cont'd)

13.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.

The pulse width modulation mode uses the com-
plete Output Compare 1 function plus the OC2R
register, and so these functionality can not be
used when the PWM mode is activated.

Procedure

To use pulse width modulation mode:

1. Load the OC2R register with the value corre-

sponding to the period of the signal using the
formula in the opposite column.

2. Load the OC1R register with the value corre-

sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.

3. Select the following in the CR1 register:

Using the OLVL1 bit, select the level to be ap-

plied to the OCMP1 pin after a successful
comparison with OC1R register.

Using the OLVL2 bit, select the level to be ap-

plied to the OCMP1 pin after a successful
comparison with OC2R register.

4. Select the following in the CR2 register:

Set OC1E bit: the OCMP1 pin is then dedicat-

ed to the output compare 1 function.

Set the PWM bit.

Select the timer clock (CC[1:0]) (see Table 15

Clock Control Bits).

If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.

If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.

The OC

R register value required for a specific tim-

ing application can be calculated using the follow-
ing formula:

Where:
t

= Signal or pulse period (in seconds)

CPU

= CPU clock frequency (in hertz)

PRESC

= Timer prescaler factor (2, 4 or 8 depend-

ing on CC[1:0] bits, see Table 15 Clock
Control Bits)

If the timer clock is an external clock the formula is:

Where:

= Signal or pulse period (in seconds)

EXT

= External timer clock frequency (in hertz)

The Output Compare 2 event causes the counter
to be initialized to FFFCh (See Figure 41)

Notes:

1. After a write instruction to the OC

iHR register,

the output compare function is inhibited until the
OC

iLR register is also written.

2. The OCF1 and OCF2 bits cannot be set by

hardware in PWM mode therefore the Output
Compare interrupt is inhibited.

3. The ICF1 bit is set by hardware when the coun-

ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.

4. In PWM mode the ICAP1 pin can not be used

to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.

5. When the Pulse Width Modulation (PWM) and

One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.

Counter

OCMP1 = OLVL2

Counter
= OC2R

OCMP1 = OLVL1

When

= OC1R

Pulse Width Modulation cycle

Counter is reset

to FFFCh

ICF1 bit is set

iR Value =

CPU

PRESC

- 5

iR =

EXT

-5

ST72334J/N, ST72314J/N, ST72124J

64/148

16-BIT TIMER (Cont'd)

13.3.4 Low Power Modes

13.3.5 Interrupts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap-
ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt
mask in the CC register is reset (RIM instruction).

13.3.6 Summary of Timer modes

See note 4 in Section 13.3.3.5 "One Pulse Mode" on page 61

See note 5 in Section 13.3.3.5 "One Pulse Mode" on page 61

See note 4 in Section 13.3.3.6 "Pulse Width Modulation Mode" on page 63

Mode

Description

WAIT

No effect on 16-bit Timer.
Timer interrupts cause the device to exit from WAIT mode.

HALT

16-bit Timer registers are frozen.

In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous
count when the MCU is woken up by an interrupt with "exit from HALT mode" capability or from the counter
reset value when the MCU is woken up by a RESET.

If an input capture event occurs on the ICAP

pin, the input capture detection circuitry is armed. Consequent-

ly, when the MCU is woken up by an interrupt with "exit from HALT mode" capability, the ICF

bit is set, and

the counter value present when exiting from HALT mode is captured into the IC

R register.

Interrupt Event

Event

Flag

Enable

Control

Bit

Exit

from

Wait

Exit

from

Halt

Input Capture 1 event/Counter reset in PWM mode

ICF1

ICIE

Yes

Input Capture 2 event

ICF2

Yes

Output Compare 1 event (not available in PWM mode)

OCF1

OCIE

Yes

Output Compare 2 event (not available in PWM mode)

OCF2

Yes

Timer Overflow event

TOF

TOIE

Yes

MODES

AVAILABLE RESOURCES

Input Capture 1

Input Capture 2

Output Compare 1 Output Compare 2

Input Capture (1 and/or 2)

Yes

Output Compare (1 and/or 2)

Yes

One Pulse Mode

Not Recommended

Partially

PWM Mode

Not Recommended

ST72334J/N, ST72314J/N, ST72124J

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16-BIT TIMER (Cont'd)

13.3.7 Register Description

Each Timer is associated with three control and
status registers, and with six pairs of data registers
(16-bit values) relating to the two input captures,
the two output compares, the counter and the al-
ternate counter.

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = ICIE

Input Capture Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the

ICF1 or ICF2 bit of the SR register is set.

Bit 6 = OCIE

Output Compare Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is generated whenever the

OCF1 or OCF2 bit of the SR register is set.

Bit 5 = TOIE

Timer Overflow Interrupt Enable.

0: Interrupt is inhibited.
1: A timer interrupt is enabled whenever the TOF

bit of the SR register is set.

Bit 4 = FOLV2

Forced Output Compare 2.

This bit is set and cleared by software.
0: No effect on the OCMP2 pin.
1: Forces the OLVL2 bit to be copied to the

OCMP2 pin, if the OC2E bit is set and even if
there is no successful comparison.

Bit 3 = FOLV1

Forced Output Compare 1.

This bit is set and cleared by software.
0: No effect on the OCMP1 pin.
1: Forces OLVL1 to be copied to the OCMP1 pin, if

the OC1E bit is set and even if there is no suc-
cessful comparison.

Bit 2 = OLVL2

Output Level 2.

This bit is copied to the OCMP2 pin whenever a
successful comparison occurs with the OC2R reg-
ister and OCxE is set in the CR2 register. This val-
ue is copied to the OCMP1 pin in One Pulse Mode
and Pulse Width Modulation mode.

Bit 1 = IEDG1

Input Edge 1.

This bit determines which type of level transition
on the ICAP1 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Bit 0 = OLVL1

Output Level 1.

The OLVL1 bit is copied to the OCMP1 pin when-
ever a successful comparison occurs with the
OC1R register and the OC1E bit is set in the CR2
register.

ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

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16-BIT TIMER (Cont'd)

CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = OC1E

Output Compare 1 Pin Enable.

This bit is used only to output the signal from the
timer on the OCMP1 pin (OLV1 in Output Com-
pare mode, both OLV1 and OLV2 in PWM and
one-pulse mode). Whatever the value of the OC1E
bit, the internal Output Compare 1 function of the
timer remains active.
0: OCMP1 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP1 pin alternate function enabled.

Bit 6 = OC2E

Output Compare 2 Pin Enable.

This bit is used only to output the signal from the
timer on the OCMP2 pin (OLV2 in Output Com-
pare mode). Whatever the value of the OC2E bit,
the internal Output Compare 2 function of the timer
remains active.
0: OCMP2 pin alternate function disabled (I/O pin

free for general-purpose I/O).

1: OCMP2 pin alternate function enabled.

Bit 5 = OPM

One Pulse Mode.

0: One Pulse Mode is not active.
1: One Pulse Mode is active, the ICAP1 pin can be

used to trigger one pulse on the OCMP1 pin; the
active transition is given by the IEDG1 bit. The
length of the generated pulse depends on the
contents of the OC1R register.

Bit 4 = PWM

Pulse Width Modulation.

0: PWM mode is not active.
1: PWM mode is active, the OCMP1 pin outputs a

programmable cyclic signal; the length of the
pulse depends on the value of OC1R register;
the period depends on the value of OC2R regis-
ter.

Bit 3, 2 = CC[1:0]

Clock Control.

The timer clock mode depends on these bits:

Table 15. Clock Control Bits

Note: If the external clock pin is not available, pro-
gramming the external clock configuration stops
the counter.

Bit 1 = IEDG2

Input Edge 2.

This bit determines which type of level transition
on the ICAP2 pin will trigger the capture.
0: A falling edge triggers the capture.
1: A rising edge triggers the capture.

Bit 0 = EXEDG

External Clock Edge.

This bit determines which type of level transition
on the external clock pin EXTCLK will trigger the
counter register.
0: A falling edge triggers the counter register.
1: A rising edge triggers the counter register.

OC1E OC2E OPM PWM CC1 CC0 IEDG2 EXEDG

Timer Clock

CC1

CC0

CPU

/ 4

CPU

/ 2

CPU

/ 8

External Clock (where

available)

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16-BIT TIMER (Cont'd)

STATUS REGISTER (SR)

Read Only

Reset Value: 0000 0000 (00h)

The three least significant bits are not used.

Bit 7 = ICF1

Input Capture Flag 1.

0: No input capture (reset value).
1: An input capture has occurred on the ICAP1 pin

or the counter has reached the OC2R value in
PWM mode. To clear this bit, first read the SR
register, then read or write the low byte of the
IC1R (IC1LR) register.

Bit 6 = OCF1

Output Compare Flag 1.

0: No match (reset value).
1: The content of the free running counter has

matched the content of the OC1R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC1R (OC1LR) reg-
ister.

Bit 5 = TOF

Timer Overflow Flag.

0: No timer overflow (reset value).
1: The free running counter rolled over from FFFFh

to 0000h. To clear this bit, first read the SR reg-
ister, then read or write the low byte of the CR
(CLR) register.

Note: Reading or writing the ACLR register does
not clear TOF.

Bit 4 = ICF2

Input Capture Flag 2.

0: No input capture (reset value).
1: An input capture has occurred on the ICAP2

pin. To clear this bit, first read the SR register,
then read or write the low byte of the IC2R
(IC2LR) register.

Bit 3 = OCF2

Output Compare Flag 2.

0: No match (reset value).
1: The content of the free running counter has

matched the content of the OC2R register. To
clear this bit, first read the SR register, then read
or write the low byte of the OC2R (OC2LR) reg-
ister.

Bit 2-0 = Reserved, forced by hardware to 0.

INPUT CAPTURE 1 HIGH REGISTER (IC1HR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
input capture 1 event).

INPUT CAPTURE 1 LOW REGISTER (IC1LR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register that contains the
low part of the counter value (transferred by the in-
put capture 1 event).

OUTPUT

COMPARE

HIGH

REGISTER

(OC1HR)

Read/Write
Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.

OUTPUT

COMPARE

LOW

REGISTER

(OC1LR)

Read/Write
Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.

ICF1

OCF1

TOF

ICF2

OCF2

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

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16-BIT TIMER (Cont'd)

OUTPUT

COMPARE

HIGH

REGISTER

(OC2HR)

Read/Write
Reset Value: 1000 0000 (80h)

This is an 8-bit register that contains the high part
of the value to be compared to the CHR register.

OUTPUT

COMPARE

LOW

REGISTER

(OC2LR)

Read/Write
Reset Value: 0000 0000 (00h)

This is an 8-bit register that contains the low part of
the value to be compared to the CLR register.

COUNTER HIGH REGISTER (CHR)

Read Only
Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part
of the counter value.

COUNTER LOW REGISTER (CLR)

Read Only
Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after accessing
the SR register clears the TOF bit.

ALTERNATE

COUNTER

HIGH

REGISTER

(ACHR)

Read Only
Reset Value: 1111 1111 (FFh)

This is an 8-bit register that contains the high part
of the counter value.

ALTERNATE

COUNTER

LOW

REGISTER

(ACLR)

Read Only
Reset Value: 1111 1100 (FCh)

This is an 8-bit register that contains the low part of
the counter value. A write to this register resets the
counter. An access to this register after an access
to SR register does not clear the TOF bit in SR
register.

INPUT CAPTURE 2 HIGH REGISTER (IC2HR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register that contains the
high part of the counter value (transferred by the
Input Capture 2 event).

INPUT CAPTURE 2 LOW REGISTER (IC2LR)

Read Only
Reset Value: Undefined

This is an 8-bit read only register that contains the
low part of the counter value (transferred by the In-
put Capture 2 event).

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

MSB

LSB

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16-BIT TIMER (Cont'd)

Table 16. 16-Bit Timer Register Map and Reset Values

Address

(Hex.)

Register

Label

Timer A: 32

Timer B: 42

CR1

Reset Value

ICIE

OCIE

TOIE

FOLV2

FOLV1

OLVL2

IEDG1

OLVL1

Timer A: 31

Timer B: 41

CR2

Reset Value

OC1E

OC2E

OPM

PWM

CC1

CC0

IEDG2

EXEDG

Timer A: 33

Timer B: 43

Reset Value

ICF1

OCF1

TOF

ICF2

OCF2

Timer A: 34

Timer B: 44

ICHR1

Reset Value

MSB

LSB

Timer A: 35

Timer B: 45

ICLR1

Reset Value

MSB

LSB

Timer A: 36

Timer B: 46

OCHR1

Reset Value

MSB

LSB

Timer A: 37

Timer B: 47

OCLR1

Reset Value

MSB

LSB

Timer A: 3E

Timer B: 4E

OCHR2

Reset Value

MSB

LSB

Timer A: 3F

Timer B: 4F

OCLR2

Reset Value

MSB

LSB

Timer A: 38

Timer B: 48

CHR

Reset Value

MSB

LSB

Timer A: 39

Timer B: 49

CLR

Reset Value

MSB

LSB

Timer A: 3A

Timer B: 4A

ACHR

Reset Value

MSB

LSB

Timer A: 3B

Timer B: 4B

ACLR

Reset Value

MSB

LSB

Timer A: 3C

Timer B: 4C

ICHR2

Reset Value

MSB

LSB

Timer A: 3D

Timer B: 4D

ICLR2

Reset Value

MSB

LSB

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13.4 SERIAL PERIPHERAL INTERFACE (SPI)

13.4.1 Introduction

The Serial Peripheral Interface (SPI) allows full-
duplex, synchronous, serial communication with
external devices. An SPI system may consist of a
master and one or more slaves or a system in
which devices may be either masters or slaves.

The SPI is normally used for communication be-
tween the microcontroller and external peripherals
or another microcontroller.

Refer to the Pin Description chapter for the device-
specific pin-out.

13.4.2 Main Features

Full duplex, three-wire synchronous transfers

Master or slave operation

Four master mode frequencies

Maximum slave mode frequency = fCPU/2.

Four programmable master bit rates

Programmable clock polarity and phase

End of transfer interrupt flag

Write collision flag protection

Master mode fault protection capability.

13.4.3 General description

The SPI is connected to external devices through
4 alternate pins:

MISO: Master In Slave Out pin

MOSI: Master Out Slave In pin

SCK: Serial Clock pin

SS: Slave select pin

A basic example of interconnections between a
single master and a single slave is illustrated on
Figure 42.

The MOSI pins are connected together as are
MISO pins. In this way data is transferred serially
between master and slave (most significant bit
first).

When the master device transmits data to a slave
device via MOSI pin, the slave device responds by
sending data to the master device via the MISO
pin. This implies full duplex transmission with both
data out and data in synchronized with the same
clock signal (which is provided by the master de-
vice via the SCK pin).

Thus, the byte transmitted is replaced by the byte
received and eliminates the need for separate
transmit-empty and receiver-full bits. A status flag
is used to indicate that the I/O operation is com-
plete.

Four possible data/clock timing relationships may
be chosen (see Figure 45) but master and slave
must be programmed with the same timing mode.

Figure 42. Serial Peripheral Interface Master/Slave

8-BIT SHIFT REGISTER

SPI

CLOCK

GENERATOR

8-BIT SHIFT REGISTER

MISO

MOSI

MISO

SCK

SLAVE

MASTER

+5V

MSBit

LSBit

MSBit

LSBit

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.4 Functional Description

Figure 42 shows the serial peripheral interface
(SPI) block diagram.

This interface contains 3 dedicated registers:

A Control Register (CR)

A Status Register (SR)

A Data Register (DR)

Refer to the CR, SR and DR registers in Section
13.4.7for the bit definitions.

13.4.4.1 Master Configuration

In a master configuration, the serial clock is gener-
ated on the SCK pin.

Procedure

Select the SPR0 & SPR1 bits to define the se-

rial clock baud rate (see CR register).

Select the CPOL and CPHA bits to define one

of the four relationships between the data
transfer and the serial clock (see Figure 45).

The SS pin must be connected to a high level

signal during the complete byte transmit se-
quence.

The MSTR and SPE bits must be set (they re-

main set only if the SS pin is connected to a
high level signal).

In this configuration the MOSI pin is a data output
and to the MISO pin is a data input.

Transmit sequence

The transmit sequence begins when a byte is writ-
ten the DR register.

The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MOSI pin most
significant bit first.

When data transfer is complete:

The SPIF bit is set by hardware

An interrupt is generated if the SPIE bit is set

and the I bit in the CCR register is cleared.

During the last clock cycle the SPIF bit is set, a
copy of the data byte received in the shift register
is moved to a buffer. When the DR register is read,
the SPI peripheral returns this buffered value.

Clearing the SPIF bit is performed by the following
software sequence:

1. An access to the SR register while the SPIF bit

is set

2. A read to the DR register.

Note: While the SPIF bit is set, all writes to the DR
register are inhibited until the SR register is read.

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.4.2 Slave Configuration

In slave configuration, the serial clock is received
on the SCK pin from the master device.

The value of the SPR0 & SPR1 bits is not used for
the data transfer.

Procedure

For correct data transfer, the slave device

must be in the same timing mode as the mas-
ter device (CPOL and CPHA bits). See Figure
45.

The SS pin must be connected to a low level

signal during the complete byte transmit se-
quence.

Clear the MSTR bit and set the SPE bit to as-

sign the pins to alternate function.

In this configuration the MOSI pin is a data input
and the MISO pin is a data output.

Transmit Sequence

The data byte is parallel loaded into the 8-bit shift
register (from the internal bus) during a write cycle
and then shifted out serially to the MISO pin most
significant bit first.

The transmit sequence begins when the slave de-
vice receives the clock signal and the most signifi-
cant bit of the data on its MOSI pin.

When data transfer is complete:

The SPIF bit is set by hardware

An interrupt is generated if SPIE bit is set and

I bit in CCR register is cleared.

Clearing the SPIF bit is performed by the following
software sequence:

1. An access to the SR register while the SPIF bit

is set.

2.A read to the DR register.

Notes: While the SPIF bit is set, all writes to the
DR register are inhibited until the SR register is
read.

The SPIF bit can be cleared during a second
transmission; however, it must be cleared before
the second SPIF bit in order to prevent an overrun
condition (see Section 13.4.4.6).

Depending on the CPHA bit, the SS pin has to be
set to write to the DR register between each data
byte transfer to avoid a write collision (see Section
13.4.4.4).

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.4.3 Data Transfer Format

During an SPI transfer, data is simultaneously
transmitted (shifted out serially) and received
(shifted in serially). The serial clock is used to syn-
chronize the data transfer during a sequence of
eight clock pulses.

The SS pin allows individual selection of a slave
device; the other slave devices that are not select-
ed do not interfere with the SPI transfer.

Clock Phase and Clock Polarity

Four possible timing relationships may be chosen
by software, using the CPOL and CPHA bits.

The CPOL (clock polarity) bit controls the steady
state value of the clock when no data is being
transferred. This bit affects both master and slave
modes.

The combination between the CPOL and CPHA
(clock phase) bits selects the data capture clock
edge.

Figure 45, shows an SPI transfer with the four
combinations of the CPHA and CPOL bits. The di-
agram may be interpreted as a master or slave
timing diagram where the SCK pin, the MISO pin,
the MOSI pin are directly connected between the
master and the slave device.

The SS pin is the slave device select input and can
be driven by the master device.

The master device applies data to its MOSI pin-
clock edge before the capture clock edge.

CPHA bit is set

The second edge on the SCK pin (falling edge if
the CPOL bit is reset, rising edge if the CPOL bit is
set) is the MSBit capture strobe. Data is latched on
the occurrence of the second clock transition.

No write collision should occur even if the SS pin
stays low during a transfer of several bytes (see
Figure 44).

CPHA bit is reset

The first edge on the SCK pin (falling edge if CPOL
bit is set, rising edge if CPOL bit is reset) is the
MSBit capture strobe. Data is latched on the oc-
currence of the first clock transition.

The SS pin must be toggled high and low between
each byte transmitted (see Figure 44).

To protect the transmission from a write collision a
low value on the SS pin of a slave device freezes
the data in its DR register and does not allow it to
be altered. Therefore the SS pin must be high to
write a new data byte in the DR without producing
a write collision.

Figure 44. CPHA / SS Timing Diagram

MOSI/ MISO

Master

Slave

(CPHA=0)

Slave

(CPHA=1)

Byte 1

Byte 2

Byte 3

VR02131A

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.4.4 Write Collision Error

A write collision occurs when the software tries to
write to the DR register while a data transfer is tak-
ing place with an external device. When this hap-
pens, the transfer continues uninterrupted; and
the software write will be unsuccessful.

Write collisions can occur both in master and slave
mode.

Note: a "read collision" will never occur since the
received data byte is placed in a buffer in which
access is always synchronous with the MCU oper-
ation.

In Slave mode

When the CPHA bit is set:

The slave device will receive a clock (SCK) edge
prior to the latch of the first data transfer. This first
clock edge will freeze the data in the slave device
DR register and output the MSBit on to the exter-
nal MISO pin of the slave device.

The SS pin low state enables the slave device but
the output of the MSBit onto the MISO pin does
not take place until the first data transfer clock
edge.

When the CPHA bit is reset:

Data is latched on the occurrence of the first clock
transition. The slave device does not have any
way of knowing when that transition will occur;
therefore, the slave device collision occurs when
software attempts to write the DR register after its
SS pin has been pulled low.

For this reason, the SS pin must be high, between
each data byte transfer, to allow the CPU to write
in the DR register without generating a write colli-
sion.

In Master mode

Collision in the master device is defined as a write
of the DR register while the internal serial clock
(SCK) is in the process of transfer.

The SS pin signal must be always high on the
master device.

WCOL bit

The WCOL bit in the SR register is set if a write
collision occurs.

No SPI interrupt is generated when the WCOL bit
is set (the WCOL bit is a status flag only).

Clearing the WCOL bit is done through a software
sequence (see Figure 46).

Figure 46. Clearing the WCOL bit (Write Collision Flag) Software Sequence

Clearing sequence after SPIF = 1 (end of a data byte transfer)

1st Step

Read SR

Read DR

Write DR

2nd Step

SPIF =0
WCOL=0

if no transfer has started

WCOL=1

if a transfer has started

Clearing sequence before SPIF = 1 (during a data byte transfer)

1st Step

2nd Step

WCOL=0

before the 2nd step

Read SR

Read DR

Note: Writing in DR register in-
stead of reading in it do not reset
WCOL bit

Read SR

THEN

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.4.5 Master Mode Fault

Master mode fault occurs when the master device
has its SS pin pulled low, then the MODF bit is set.

Master mode fault affects the SPI peripheral in the
following ways:

The MODF bit is set and an SPI interrupt is

generated if the SPIE bit is set.

The SPE bit is reset. This blocks all output

from the device and disables the SPI periph-
eral.

The MSTR bit is reset, thus forcing the device

into slave mode.

Clearing the MODF bit is done through a software
sequence:

1. A read or write access to the SR register while

the MODF bit is set.

2. A write to the CR register.

Notes: To avoid any multiple slave conflicts in the
case of a system comprising several MCUs, the
SS pin must be pulled high during the clearing se-
quence of the MODF bit. The SPE and MSTR bits

may be restored to their original state during or af-
ter this clearing sequence.

Hardware does not allow the user to set the SPE
and MSTR bits while the MODF bit is set except in
the MODF bit clearing sequence.

In a slave device the MODF bit can not be set, but
in a multi master configuration the device can be in
slave mode with this MODF bit set.

The MODF bit indicates that there might have
been a multi-master conflict for system control and
allows a proper exit from system operation to a re-
set or default system state using an interrupt rou-
tine.

13.4.4.6 Overrun Condition

An overrun condition occurs when the master de-
vice has sent several data bytes and the slave de-
vice has not cleared the SPIF bit issuing from the
previous data byte transmitted.

In this case, the receiver buffer contains the byte
sent after the SPIF bit was last cleared. A read to
the DR register returns this byte. All other bytes
are lost.

This condition is not detected by the SPI peripher-
al.

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.4.7 Single Master and Multimaster Configurations

There are two types of SPI systems:

Single Master System

Multimaster System

Single Master System

A typical single master system may be configured,
using an MCU as the master and four MCUs as
slaves (see Figure 47).

The master device selects the individual slave de-
vices by using four pins of a parallel port to control
the four SS pins of the slave devices.

The SS pins are pulled high during reset since the
master device ports will be forced to be inputs at
that time, thus disabling the slave devices.

Note: To prevent a bus conflict on the MISO line
the master allows only one active slave device
during a transmission.

For more security, the slave device may respond
to the master with the received data byte. Then the
master will receive the previous byte back from the
slave device if all MISO and MOSI pins are con-
nected and the slave has not written its DR regis-
ter.

Other transmission security methods can use
ports for handshake lines or data bytes with com-
mand fields.

Multi-master System

A multi-master system may also be configured by
the user. Transfer of master control could be im-
plemented using a handshake method through the
I/O ports or by an exchange of code messages
through the serial peripheral interface system.

The multi-master system is principally handled by
the MSTR bit in the CR register and the MODF bit
in the SR register.

Figure 47. Single Master Configuration

MISO

MOSI

MISO

SCK

Ports

Slave

MCU

Slave

MCU

Slave

MCU

Slave

MCU

Master

MCU

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SERIAL PERIPHERAL INTERFACE (Cont'd)

13.4.7 Register Description

CONTROL REGISTER (CR)

Read/Write

Reset Value: 0000xxxx (0xh)

Bit 7 = SPIE

Serial peripheral interrupt enable.

This bit is set and cleared by software.
0: Interrupt is inhibited
1: An SPI interrupt is generated whenever SPIF=1

or MODF=1 in the SR register

Bit 6 = SPE

Serial peripheral output enable.

This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 13.4.4.5 "Master Mode Fault" on
page 77).
0: I/O port connected to pins
1: SPI alternate functions connected to pins

The SPE bit is cleared by reset, so the SPI periph-
eral is not initially connected to the external pins.

Bit 5 = SPR2

Divider Enable.

this bit is set and cleared by software and it is
cleared by reset. It is used with the SPR[1:0] bits to
set the baud rate. Refer to Table 17.
0: Divider by 2 enabled
1: Divider by 2 disabled

Bit 4 = MSTR

Master.

This bit is set and cleared by software. It is also
cleared by hardware when, in master mode, SS=0
(see Section 13.4.4.5 "Master Mode Fault" on
page 77).
0: Slave mode is selected
1: Master mode is selected, the function of the

SCK pin changes from an input to an output and
the functions of the MISO and MOSI pins are re-
versed.

Bit 3 = CPOL

Clock polarity.

This bit is set and cleared by software. This bit de-
termines the steady state of the serial Clock. The
CPOL bit affects both the master and slave
modes.
0: The steady state is a low value at the SCK pin.
1: The steady state is a high value at the SCK pin.

Bit 2 = CPHA

Clock phase.

This bit is set and cleared by software.
0: The first clock transition is the first data capture

edge.

1: The second clock transition is the first capture

edge.

Bit 1:0 = SPR[1:0]

Serial peripheral rate.

These bits are set and cleared by software.Used
with the SPR2 bit, they select one of six baud rates
to be used as the serial clock when the device is a
master.

These 2 bits have no effect in slave mode.

Table 17. Serial Peripheral Baud Rate

SPIE

SPE

SPR2

MSTR

CPOL

CPHA

SPR1

SPR0

Serial Clock

SPR2

SPR1

SPR0

fCPU/2

fCPU/8

fCPU/16

fCPU/32

fCPU/64

fCPU/128

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SERIAL PERIPHERAL INTERFACE (Cont'd)

STATUS REGISTER (SR)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7 = SPIF

Serial Peripheral data transfer flag.

This bit is set by hardware when a transfer has
been completed. An interrupt is generated if
SPIE=1 in the CR register. It is cleared by a soft-
ware sequence (an access to the SR register fol-
lowed by a read or write to the DR register).
0: Data transfer is in progress or has been ap-

proved by a clearing sequence.

1: Data transfer between the device and an exter-

nal device has been completed.

Note: While the SPIF bit is set, all writes to the DR
register are inhibited.

Bit 6 = WCOL

Write Collision status.

This bit is set by hardware when a write to the DR
register is done during a transmit sequence. It is
cleared by a software sequence (see Figure 46).
0: No write collision occurred
1: A write collision has been detected

Bit 5 = Unused.

Bit 4 = MODF

Mode Fault flag.

This bit is set by hardware when the SS pin is
pulled low in master mode (see Section 13.4.4.5
"Master Mode Fault" on page 77). An SPI interrupt
can be generated if SPIE=1 in the CR register.
This bit is cleared by a software sequence (An ac-
cess to the SR register while MODF=1 followed by
a write to the CR register).
0: No master mode fault detected
1: A fault in master mode has been detected

Bits 3-0 = Unused.

DATA I/O REGISTER (DR)

Read/Write

Reset Value: Undefined

The DR register is used to transmit and receive
data on the serial bus. In the master device only a
write to this register will initiate transmission/re-
ception of another byte.

Notes: During the last clock cycle the SPIF bit is
set, a copy of the received data byte in the shift
register is moved to a buffer. When the user reads
the serial peripheral data I/O register, the buffer is
actually being read.

Warning:

A write to the DR register places data directly into
the shift register for transmission.

A write to the the DR register returns the value lo-
cated in the buffer and not the contents of the shift
register (See Figure 43 ).

SPIF

WCOL

MODF

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13.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

13.5.1 Introduction

The Serial Communications Interface (SCI) offers
a flexible means of full-duplex data exchange with
external equipment requiring an industry standard
NRZ asynchronous serial data format. The SCI of-
fers a very wide range of baud rates using two
baud rate generator systems.

13.5.2 Main Features

Full duplex, asynchronous communications

NRZ standard format (Mark/Space)

Dual baud rate generator systems

Independently

programmable

transmit

and

receive baud rates up to 250K baud.

Programmable data word length (8 or 9 bits)

Receive buffer full, Transmit buffer empty and
End of Transmission flags

Two receiver wake-up modes:

Address bit (MSB)

Idle line

Muting function for multiprocessor configurations

Separate

enable bits for Transmitter and

Receiver

Three error detection flags:

Overrun error

Noise error

Frame error

Five interrupt sources with flags:

Transmit data register empty

Transmission complete

Receive data register full

Idle line received

Overrun error detected

13.5.3 General Description

The interface is externally connected to another
device by two pins (see Figure 49):

TDO: Transmit Data Output. When the transmit-

ter is disabled, the output pin returns to its I/O
port configuration. When the transmitter is ena-
bled and nothing is to be transmitted, the TDO
pin is at high level.

RDI: Receive Data Input is the serial data input.

Oversampling techniques are used for data re-
covery by discriminating between valid incoming
data and noise.

Through this pins, serial data is transmitted and re-
ceived as frames comprising:

An Idle Line prior to transmission or reception

A start bit

A data word (8 or 9 bits) least significant bit first

A Stop bit indicating that the frame is complete.

This interface usestwo types of baud rate generator:

A conventional type for commonly-used baud

rates,

An extended type with a prescaler offering a very

wide range of baud rates even with non-standard
oscillator frequencies.

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

13.5.4 Functional Description

The block diagram of the Serial Control Interface,
is shown in Figure 48. It contains 6 dedicated reg-
isters:

Two control registers (CR1 & CR2)

A status register (SR)

A baud rate register (BRR)

An extended prescaler receiver register (ERPR)

Anextended prescaler transmitter register (ETPR)

Refer to the register descriptions in Section
13.5.7for the definitions of each bit.

13.5.4.1 Serial Data Format

Word length may be selected as being either 8 or 9
bits by programming the M bit in the CR1 register
(see Figure 48).

The TDO pin is in low state during the start bit.

The TDO pin is in high state during the stop bit.

An Idle character is interpreted as an entire frame
of "1"s followed by the start bit of the next frame
which contains data.

A Break character is interpreted on receiving "0"s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra "1" bit to acknowledge the start bit.

Transmission and reception are driven by their
own baud rate generator.

Figure 49. Word length programming

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Bit8

Start

Bit

Stop

Bit

Start

Bit

Idle Frame

Bit0

Bit1

Bit2

Bit3

Bit4

Bit5

Bit6

Bit7

Start

Bit

Stop

Bit

Start

Bit

Start

Bit

Idle Frame

Start

Bit

9-bit Word length (M bit is set)

8-bit Word length (M bit is reset)

Possible

Parity

Bit

Possible

Parity

Bit

Break Frame

Start

Bit

Extra

'1'

Data Frame

Break Frame

Start

Bit

Extra

'1'

Data Frame

Next Data Frame

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

13.5.4.2 Transmitter

The transmitter can send data words of either 8 or
9 bits depending on the M bit status. When the M
bit is set, word length is 9 bits and the 9th bit (the
MSB) has to be stored in the T8 bit in the CR1 reg-
ister.

Character Transmission

During an SCI transmission, data shifts out least
significant bit first on the TDO pin. In this mode,
the DR register consists of a buffer (TDR) between
the internal bus and the transmit shift register (see
Figure 48).

Procedure

Select the M bit to define the word length.

Select the desired baud rate using the BRR and

the ETPR registers.

Set the TE bit to assign the TDO pin to the alter-

nate function and to send a idle frame as first
transmission.

Access the SR register and write the data to

send in the DR register (this sequence clears the
TDRE bit). Repeat this sequence for each data to
be transmitted.

Clearing the TDRE bit is always performed by the
following software sequence:
1. An access to the SR register
2. A write to the DR register

The TDRE bit is set by hardware and it indicates:

The TDR register is empty.

The data transfer is beginning.

The next data can be written in the DR register

without overwriting the previous data.

This flag generates an interrupt if the TIE bit is set
and the I bit is cleared in the CCR register.

When a transmission is taking place, a write in-
struction to the DR register stores the data in the
TDR register and which is copied in the shift regis-
ter at the end of the current transmission.

When no transmission is taking place, a write in-
struction to the DR register places the data directly
in the shift register, the data transmission starts,
and the TDRE bit is immediately set.

When a frame transmission is complete (after the
stop bit or after the break frame) the TC bit is set
and an interrupt is generated if the TCIE is set and
the I bit is cleared in the CCR register.

Clearing the TC bit is performed by the following
software sequence:
1. An access to the SR register
2. A write to the DR register

Note: The TDRE and TC bits are cleared by the
same software sequence.

Break Characters

Setting the SBK bit loads the shift register with a
break character. The break frame length depends
on the M bit (see Figure 49).

As long as the SBK bit is set, the SCI send break
frames to the TDO pin. After clearing this bit by
software the SCI insert a logic 1 bit at the end of
the last break frame to guarantee the recognition
of the start bit of the next frame.

Idle Characters

Setting the TE bit drives the SCI to send an idle
frame before the first data frame.

Clearing and then setting the TE bit during a trans-
mission sends an idle frame after the current word.

Note: Resetting and setting the TE bit causes the
data in the TDR register to be lost. Therefore the
best time to toggle the TE bit is when the TDRE bit
is set i.e. before writing the next byte in the DR.

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

13.5.4.3 Receiver

The SCI can receive data words of either 8 or 9
bits. When the M bit is set, word length is 9 bits
and the MSB is stored in the R8 bit in the CR1 reg-
ister.

Character reception

During a SCI reception, data shifts in least signifi-
cant bit first through the RDI pin. In this mode, DR
register consists in a buffer (RDR) between the in-
ternal bus and the received shift register (see Fig-
ure 48).

Procedure

Select the M bit to define the word length.

Select the desired baud rate using the BRR and

the ERPR registers.

Set the RE bit, this enables the receiver which

begins searching for a start bit.

When a character is received:

The RDRF bit is set. It indicates that the content

of the shift register is transferred to the RDR.

An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The error flags can be set if a frame error, noise

or an overrun error has been detected during re-
ception.

Clearing the RDRF bit is performed by the following
software sequence done by:

1. An access to the SR register

2. A read to the DR register.

The RDRF bit must be cleared before the end of the
reception of the next character to avoid an overrun
error.

Break Character

When a break character is received, the SPI han-
dles it as a framing error.

Idle Character

When a idle frame is detected, there is the same
procedure as a data received character plus an in-
terrupt if the ILIE bit is set and the I bit is cleared in
the CCR register.

Overrun Error

An overrun error occurs when a character is re-
ceived when RDRF has not been reset. Data can
not be transferred from the shift register to the
TDR register as long as the RDRF bit is not
cleared.

When a overrun error occurs:

The OR bit is set.

The RDR content will not be lost.

The shift register will be overwritten.

An interrupt is generated if the RIE bit is set and

the I bit is cleared in the CCR register.

The OR bit is reset by an access to the SR register
followed by a DR register read operation.

Noise Error

Oversampling techniques are used for data recov-
ery by discriminating between valid incoming data
and noise.

When noise is detected in a frame:

The NF is set at the rising edge of the RDRF bit.

Data is transferred from the Shift register to the

DR register.

No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself
generates an interrupt.

The NF bit is reset by a SR register read operation
followed by a DR register read operation.

Framing Error

A framing error is detected when:

The stop bit is not recognized on reception at the

expected time, following either a de-synchroni-
zation or excessive noise.

A break is received.

When the framing error is detected:

the FE bit is set by hardware

Data is transferred from the Shift register to the

DR register.

No interrupt is generated. However this bit rises

at the same time as the RDRF bit which itself
generates an interrupt.

The FE bit is reset by a SR register read operation
followed by a DR register read operation.

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

13.5.4.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx
and Tx) are set independently and calculated as
follows:

with:

PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits)

TR = 1, 2, 4, 8, 16, 32, 64,128

(see SCT0, SCT1 & SCT2 bits)

RR = 1, 2, 4, 8, 16, 32, 64,128

(see SCR0,SCR1 & SCR2 bits)

All this bits are in the BRR register.

Example: If f

CPU

is 8 MHz (normal mode) and if

PR=13 and TR=RR=1, the transmit and receive
baud rates are 19200 baud.

Note: the baud rate registers MUST NOT be
changed while the transmitter or the receiver is en-
abled.

13.5.4.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine
tuning on the baud rate, using a 255 value prescal-
er, whereas the conventional Baud Rate Genera-
tor retains industry standard software compatibili-
ty.

The extended baud rate generator block diagram
is described in the Figure 50.

The output clock rate sent to the transmitter or to
the receiver will be the output from the 16 divider
divided by a factor ranging from 1 to 255 set in the
ERPR or the ETPR register.

Note: the extended prescaler is activated by set-
ting the ETPR or ERPR register to a value other

than zero. The baud rates are calculated as fol-
lows:

with:

ETPR = 1,..,255 (see ETPR register)

ERPR = 1,.. 255 (see ERPR register)

13.5.4.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira-
ble that only the intended message recipient
should actively receive the full message contents,
thus reducing redundant SCI service overhead for
all non addressed receivers.

The non addressed devices may be placed in
sleep mode by means of the muting function.

Setting the RWU bit by software puts the SCI in
sleep mode:

All the reception status bits can not be set.

All the receive interrupt are inhibited.

A muted receiver may be awakened by one of the
following two ways:

by Idle Line detection if the WAKE bit is reset,

by Address Mark detection if the WAKE bit is set.

Receiver wakes-up by Idle Line detection when
the Receive line has recognised an Idle Frame.
Then the RWU bit is reset by hardware but the
IDLE bit is not set.

Receiver wakes-up by Address Mark detection
when it received a "1" as the most significant bit of
a word, thus indicating that the message is an ad-
dress. The reception of this particular word wakes
up the receiver, resets the RWU bit and sets the
RDRF bit, which allows the receiver to receive this
word normally and to use it as an address word.

Tx =

(32

PR)

CPU

Rx =

(32

PR)

CPU

Tx =

ETPR

CPU

Rx =

ERPR

CPU

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

13.5.7 Register Description

STATUS REGISTER (SR)

Read Only

Reset Value: 1100 0000 (C0h)

Bit 7 = TDRE

Transmit data register empty.

This bit is set by hardware when the content of the
TDR register has been transferred into the shift
register. An interrupt is generated if the TIE =1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
0: Data is not transferred to the shift register
1: Data is transferred to the shift register

Note: data will not be transferred to the shift regis-
ter as long as the TDRE bit is not reset.

Bit 6 = TC

Transmission complete.

This bit is set by hardware when transmission of a
frame containing Data, a Preamble or a Break is
complete. An interrupt is generated if TCIE=1 in
the CR2 register. It is cleared by a software se-
quence (an access to the SR register followed by a
write to the DR register).
0: Transmission is not complete
1: Transmission is complete

Bit 5 = RDRF

Received data ready flag.

This bit is set by hardware when the content of the
RDR register has been transferred into the DR
register. An interrupt is generated if RIE=1 in the
CR2 register. It is cleared by hardware when
RE=0 or by a software sequence (an access to the
SR register followed by a read to the DR register).
0: Data is not received
1: Received data is ready to be read

Bit 4 = IDLE

Idle line detect.

This bit is set by hardware when a Idle Line is de-
tected. An interrupt is generated if the ILIE=1 in
the CR2 register. It is cleared by hardware when
RE=0 by a software sequence (an access to the
SR register followed by a read to the DR register).
0: No Idle Line is detected
1: Idle Line is detected

Note: The IDLE bit will not be set again until the
RDRF bit has been set itself (i.e. a new idle line oc-
curs). This bit is not set by an idle line when the re-
ceiver wakes up from wake-up mode.

Bit 3 = OR

Overrun error.

This bit is set by hardware when the word currently
being received in the shift register is ready to be
transferred into the RDR register while RDRF=1.
An interrupt is generated if RIE=1 in the CR2 reg-
ister. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Overrun error
1: Overrun error is detected

Note: When this bit is set RDR register content will
not be lost but the shift register will be overwritten.

Bit 2 = NF

Noise flag.

This bit is set by hardware when noise is detected
on a received frame. It is cleared by hardware
when RE=0 by a software sequence (an access to
the SR register followed by a read to the DR regis-
ter).
0: No noise is detected
1: Noise is detected

Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt.

Bit 1 = FE

Framing error.

This bit is set by hardware when a de-synchroniza-
tion, excessive noise or a break character is de-
tected. It is cleared by hardware when RE=0 by a
software sequence (an access to the SR register
followed by a read to the DR register).
0: No Framing error is detected
1: Framing error or break character is detected

Note: This bit does not generate interrupt as it ap-
pears at the same time as the RDRF bit which it-
self generates an interrupt. If the word currently
being transferred causes both frame error and
overrun error, it will be transferred and only the OR
bit will be set.

Bit 0 = Unused.

TDRE

RDRF

IDLE

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

CONTROL REGISTER 1 (CR1)

Read/Write

Reset Value: Undefined

Bit 7 = R8

Receive data bit 8.

This bit is used to store the 9th bit of the received
word when M=1.

Bit 6 = T8

Transmit data bit 8.

This bit is used to store the 9th bit of the transmit-
ted word when M=1.

Bit 4 = M

Word length.

This bit determines the word length. It is set or
cleared by software.
0: 1 Start bit, 8 Data bits, 1 Stop bit
1: 1 Start bit, 9 Data bits, 1 Stop bit

Bit 3 = WAKE

Wake-Up method.

This bit determines the SCI Wake-Up method, it is
set or cleared by software.
0: Idle Line
1: Address Mark

CONTROL REGISTER 2 (CR2)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = TIE

Transmitter interrupt enable.

This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever

TDRE=1 in the SR register.

Bit 6 = TCIE

Transmission complete interrupt ena-

ble

This bit is set and cleared by software.
0: interrupt is inhibited

1: An SCI interrupt is generated whenever TC=1 in

the SR register

Bit 5 = RIE

Receiver interrupt enable.

This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever OR=1

or RDRF=1 in the SR register

Bit 4 = ILIE

Idle line interrupt enable.

This bit is set and cleared by software.
0: interrupt is inhibited
1: An SCI interrupt is generated whenever IDLE=1

in the SR register.

Bit 3 = TE

Transmitter enable.

This bit enables the transmitter and assigns the
TDO pin to the alternate function. It is set and
cleared by software.
0: Transmitter is disabled, the TDO pin is back to

the I/O port configuration.

1: Transmitter is enabled

Note: during transmission, a "0" pulse on the TE
bit ("0" followed by "1") sends a preamble after the
current word.

Bit 2 = RE

Receiver enable.

This bit enables the receiver. It is set and cleared
by software.
0: Receiver is disabled, it resets the RDRF, IDLE,

OR, NF and FE bits of the SR register.

1: Receiver is enabled and begins searching for a

start bit.

Bit 1 = RWU

Receiver wake-up.

This bit determines if the SCI is in mute mode or
not. It is set and cleared by software and can be
cleared by hardware when a wake-up sequence is
recognized.
0: Receiver in active mode
1: Receiver in mute mode

Bit 0 = SBK

Send break.

This bit set is used to send break characters. It is
set and cleared by software.
0: No break character is transmitted
1: Break characters are transmitted

Note: If the SBK bit is set to "1" and then to "0", the
transmitter will send a BREAK word at the end of
the current word.

WAK E

TIE

TCIE

RIE

ILIE

RWU

SBK

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

DATA REGISTER (DR)

Read/Write

Reset Value: Undefined

Contains the Received or Transmitted data char-
acter, depending on whether it is read from or writ-
ten to.

The Data register performs a double function (read
and write) since it is composed of two registers,
one for transmission (TDR) and one for reception
(RDR).
The TDR register provides the parallel interface
between the internal bus and the output shift reg-
ister (see Figure 48).
The RDR register provides the parallel interface
between the input shift register and the internal
bus (see Figure 48).

BAUD RATE REGISTER (BRR)

Read/Write

Reset Value: 00xx xxxx (XXh)

Bit 7:6= SCP[1:0]

First SCI Prescaler

These 2 prescaling bits allow several standard
clock division ranges:

Bit 5:3 = SCT[2:0]

SCI Transmitter rate divisor

These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the transmit rate clock in convention-
al Baud Rate Generator mode.

Note: this TR factor is used only when the ETPR
fine tuning factor is equal to 00h; otherwise, TR is
replaced by the ETPR dividing factor.

Bit 2:0 = SCR[2:0]

SCI Receiver rate divisor.

These 3 bits, in conjunction with the SCP1 & SCP0
bits define the total division applied to the bus
clock to yield the receive rate clock in conventional
Baud Rate Generator mode.

Note: this RR factor is used only when the ERPR
fine tuning factor is equal to 00h; otherwise, RR is
replaced by the ERPR dividing factor.

DR7

DR6

DR5

DR4

DR3

DR2

DR1

DR0

SCP1

SCP0

SCT2

SCT1

SCT0

SCR2

SCR1

SCR0

PR Prescaling factor

SCP1

SCP0

TR dividi ng factor

SCT2

SCT1

SCT0

128

RR dividi ng factor

SCR2

SCR1

SCR0

128

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SERIAL COMMUNICATIONS INTERFACE (Cont'd)

EXTENDED RECEIVE PRESCALER DIVISION
REGISTER (ERPR)

Read/Write

Reset Value: 0000 0000 (00h)

Allows setting of the Extended Prescaler rate divi-
sion factor for the receive circuit.

Bit 7:1 = ERPR[7:0]

8-bit Extended Receive Pres-

caler Register.

The extended Baud Rate Generator is activated
when a value different from 00h is stored in this
register. Therefore the clock frequency issued
from the 16 divider (see Figure 50) is divided by
the binary factor set in the ERPR register (in the
range 1 to 255).

The extended baud rate generator is not used af-
ter a reset.

EXTENDED TRANSMIT PRESCALER DIVISION
REGISTER (ETPR)

Read/Write

Reset Value:0000 0000 (00h)

Allows setting of the External Prescaler rate divi-
sion factor for the transmit circuit.

Bit 7:1 = ETPR[7:0]

8-bit Extended Transmit Pres-

caler Register.

The extended baud rate generator is not used af-
ter a reset.

Table 19. SCI Register Map and Reset Values

ERPR

ETPR

ETP R

ETPR

ETP R

ETPR

ETP R

ETPR

ETP R

Address

(Hex.)

Register

Label

0050h

SCISR
Reset Value

TDRE

RDRF

IDLE

0051h

SCIDR
Reset Value

MSB

LSB

0052h

SCIBRR
Reset Value

SOG

VPOL

2FHDET

HVSEL

VCORDIS

CLPINV

BLKINV

0053h

SCICR1
Reset Value

WAKE

0054h

SCICR2
Reset Value

TIE

TCIE

RIE

ILIE

RWU

SBK

0055h

SCIPBRR
Reset Value

MSB

LSB

0057h

SCIPBRT
Reset Value

MSB

LSB

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13.6 8-BIT A/D CONVERTER (ADC)

13.6.1 Introduction

The on-chip Analog to Digital Converter (ADC) pe-
ripheral is a 8-bit, successive approximation con-
verter with internal sample and hold circuitry. This
peripheral has up to 16 multiplexed analog input
channels (refer to device pin out description) that
allow the peripheral to convert the analog voltage
levels from up to 16 different sources.

The result of the conversion is stored in a 8-bit
Data Register. The A/D converter is controlled
through a Control/Status Register.

13.6.2 Main Features

8-bit conversion

Up to 16 channels with multiplexed input

Linear successive approximation

Data register (DR) which contains the results

Conversion complete status flag

On/off bit (to reduce consumption)

The block diagram is shown in Figure 51.

13.6.3 Functional Description

13.6.3.1 Analog Power Supply

DDA

and V

SSA

are the high and low level refer-

ence voltage pins. In some devices (refer to device
pin out description) they are internally connected
to the V

and V

pins.

Conversion accuracy may therefore be impacted
by voltage drops and noise in the event of heavily
loaded or badly decoupled power supply lines.

See electrical characteristics section for more de-
tails.

Figure 51. ADC Block Diagram

CH2

CH1

CH3

COCO

ADON

CH0

ADCCSR

AIN0

AIN1

ANALOG TO DIGITAL

CONVERTER

AINx

ANALOG

MUX

ADC

ADCDR

DIV 2

ADC

CPU

HOLD CONTROL

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8-BIT A/D CONVERTER (ADC) (Cont'd)

13.6.3.2 Digital A/D Conversion Result

The conversion is monotonic, meaning that the re-
sult never decreases if the analog input does not
and never increases if the analog input does not.

If the input voltage (V

AIN

) is greater than or equal

to V

DDA

(high-level voltage reference) then the

conversion result in the DR register is FFh (full
scale) without overflow indication.

If input voltage (V

AIN

) is lower than or equal to

SSA

(low-level voltage reference) then the con-

version result in the DR register is 00h.

The A/D converter is linear and the digital result of
the conversion is stored in the ADCDR register.
The accuracy of the conversion is described in the
parametric section.

AIN

is the maximum recommended impedance

for an analog input signal. If the impedance is too
high, this will result in a loss of accuracy due to
leakage and sampling not being completed in the
alloted time.

13.6.3.3 A/D Conversion Phases

The A/D conversion is based on two conversion
phases as shown in Figure 52:

Sample capacitor loading [duration: t

LOAD

]

During this phase, the V

AIN

input voltage to be

measured is loaded into the C

ADC

sample

capacitor.

A/D conversion [duration: t

CONV

]

During this phase, the A/D conversion is
computed (8 successive approximations cycles)
and the C

ADC

sample capacitor is disconnected

from the analog input pin to get the optimum
analog to digital conversion accuracy.

While the ADC is on, these two phases are contin-
uously repeated.

At the end of each conversion, the sample capaci-
tor is kept loaded with the previous measurement
load. The advantage of this behaviour is that it
minimizes the current consumption on the analog
pin in case of single input channel measurement.

13.6.3.4 Software Procedure

Refer to the control/status register (CSR) and data
register (DR) in Section 13.6.6 for the bit defini-
tions and to Figure 52 for the timings.

ADC Configuration

The total duration of the A/D conversion is 12 ADC
clock periods (1/f

ADC

=2/f

CPU

The analog input ports must be configured as in-
put, no pull-up, no interrupt. Refer to the «I/O
ports» chapter. Using these pins as analog inputs
does not affect the ability of the port to be read as
a logic input.

In the CSR register:

Select the CH[3:0] bits to assign the analog

channel to be converted.

ADC Conversion

In the CSR register:

Set the ADON bit to enable the A/D converter

and to start the first conversion. From this time

on, the ADC performs a continuous conver-

sion of the selected channel.

When a conversion is complete

The COCO bit is set by hardware.
No interrupt is generated.
The result is in the DR register and remains

valid until the next conversion has ended.

A write to the CSR register (with ADON set) aborts
the current conversion, resets the COCO bit and
starts a new conversion.

Figure 52. ADC Conversion Timings

13.6.4 Low Power Modes

Note: The A/D converter may be disabled by reset-
ting the ADON bit. This feature allows reduced
power consumption when no conversion is needed
and between single shot conversions.

13.6.5 Interrupts

None

Mode

Description

WAIT

No effect on A/D Converter

HALT

A/D Converter disabled.
After wakeup from Halt mode, the A/D Con-
verter requires a stabilisation time before ac-
curate conversions can be performed.

ADCCSR WRITE

ADON

COCO BIT SET

LOAD

CONV

OPERATION

HOLD
CONTROL

ST72334J/N, ST72314J/N, ST72124J

97/148

8-BIT A/D CONVERTER (ADC) (Cont'd)

13.6.6 Register Description

CONTROL/STATUS REGISTER (CSR)

Read/Write

Reset Value: 0000 0000 (00h)

Bit 7 = COCO

Conversion Complete

This bit is set by hardware. It is cleared by soft-
ware reading the result in the DR register or writing
to the CSR register.
0: Conversion is not complete
1: Conversion can be read from the DR register

Bit 6 = Reserved.

must always be cleared.

Bit 5 = ADON

A/D Converter On

This bit is set and cleared by software.
0: A/D converter is switched off
1: A/D converter is switched on

Bit 4 = Reserved.

must always be cleared.

Bit 3:0 = CH[3:0]

Channel Selection

These bits are set and cleared by software. They
select the analog input to convert.

*Note: The number of pins AND the channel selec-
tion varies according to the device. Refer to the de-
vice pinout.

DATA REGISTER (DR)

Read Only

Reset Value: 0000 0000 (00h)

Bit 7:0 = D[7:0]

Analog Converted Value

This register contains the converted analog value
in the range 00h to FFh.

Note: Reading this register reset the COCO flag.

COCO

ADON

CH3

CH2

CH1

CH0

Channel Pin*

CH3

CH2

CH1

CH0

AIN0

AIN1

AIN2

AIN3

AIN4

AIN5

AIN6

AIN7

AIN8

AIN9

AIN10

AIN11

AIN12

AIN13

AIN14

AIN15

ST72334J/N, ST72314J/N, ST72124J

99/148

14 INSTRUCTION SET

14.1 ST7 ADDRESSING MODES

The ST7 Core features 17 different addressing
modes which can be classified in 7 main groups:

The ST7 Instruction set is designed to minimize
the number of bytes required per instruction: To do

so, most of the addressing modes may be subdi-
vided in two sub-modes called long and short:

Long addressing mode is more powerful be-

cause it can use the full 64 Kbyte address space,
however it uses more bytes and more CPU cy-
cles.

Short addressing mode is less powerful because

it can generally only access page zero (0000h -
00FFh range), but the instruction size is more
compact, and faster. All memory to memory in-
structions use short addressing modes only
(CLR, CPL, NEG, BSET, BRES, BTJT, BTJF,
INC, DEC, RLC, RRC, SLL, SRL, SRA, SWAP)

The ST7 Assembler optimizes the use of long and
short addressing modes.

Table 21. ST7 Addressing Mode Overview

Note 1. At the time the instruction is executed, the Program Counter (PC) points to the instruction follow-
ing JRxx.

Addressing Mode

Example

Inherent

nop

Immediate

ld A,#$55

Direct

ld A,$55

Indexed

ld A,($55,X)

Indirect

ld A,([$55],X)

Relative

jrne loop

Bit operation

bset

byte,#5

Mode

Syntax

Destination/

Source

Pointer

Address

(Hex.)

Pointer

Size

(Hex.)

Length

(Bytes)

Inherent

nop

+ 0

Immediate

ld A,#$55

+ 1

Short

Direct

ld A,$10

00..FF

+ 1

Long

Direct

ld A,$1000

0000..FFFF

+ 2

No Offset

Direct

Indexed

ld A,(X)

00..FF

+ 0 (with X register)
+ 1 (with Y register)

Short

Direct

Indexed

ld A,($10,X)

00..1FE

+ 1

Long

Direct

Indexed

ld A,($1000,X)

0000..FFFF

+ 2

Short

Indirect

ld A,[$10]

00..FF

byte

+ 2

Long

Indirect

ld A,[$10.w]

0000..FFFF

00..FF

word

+ 2

Short

Indirect

Indexed

ld A,([$10],X)

00..1FE

00..FF

byte

+ 2

Long

Indirect

Indexed

ld A,([$10.w],X)

0000..FFFF

00..FF

word

+ 2

Relative

Direct

jrne loop

PC-128/PC+127

+ 1

Relative

Indirect

jrne [$10]

PC-128/PC+127

00..FF

byte

+ 2

Bit

Direct

bset $10,#7

00..FF

+ 1

Bit

Indirect

bset [$10],#7

00..FF

byte

+ 2

Bit

Direct

Relative

btjt $10,#7,skip

00..FF

+ 2

Bit

Indirect

Relative

btjt [$10],#7,skip 00..FF

00..FF

byte

+ 3

ST72334J/N, ST72314J/N, ST72124J

100/148

ST7 ADDRESSING MODES (Cont'd)

14.1.1 Inherent

All Inherent instructions consist of a single byte.
The opcode fully specifies all the required informa-
tion for the CPU to process the operation.

14.1.2 Immediate

Immediate instructions have two bytes, the first
byte contains the opcode, the second byte con-
tains the operand value.

14.1.3 Direct

In Direct instructions, the operands are referenced
by their memory address.

The direct addressing mode consists of two sub-
modes:

Direct (short)

The address is a byte, thus requires only one byte
after the opcode, but only allows 00 - FF address-
ing space.

Direct (long)

The address is a word, thus allowing 64 Kbyte ad-
dressing space, but requires 2 bytes after the op-
code.

14.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its
memory address, which is defined by the unsigned
addition of an index register (X or Y) with an offset.

The indirect addressing mode consists of three
sub-modes:

Indexed (No Offset)

There is no offset, (no extra byte after the opcode),
and allows 00 - FF addressing space.

Indexed (Short)

The offset is a byte, thus requires only one byte af-
ter the opcode and allows 00 - 1FE addressing
space.

Indexed (long)

The offset is a word, thus allowing 64 Kbyte ad-
dressing space and requires 2 bytes after the op-
code.

14.1.5 Indirect (Short, Long)

The required data byte to do the operation is found
by its memory address, located in memory (point-
er).

The pointer address follows the opcode. The indi-
rect addressing mode consists of two sub-modes:

Indirect (short)

The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - FF addressing space, and
requires 1 byte after the opcode.

Indirect (long)

The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

Inherent Instruction

Function

NOP

No operation

TRAP

S/W Interrupt

WFI

Wait For Interrupt (Low Power
Mode)

HALT

Halt Oscillator (Lowest Power
Mode)

RET

Sub-routine Return

IRET

Interrupt Sub-routine Return

SIM

Set Interrupt Mask

RIM

Reset Interrupt Mask

SCF

Set Carry Flag

RCF

Reset Carry Flag

RSP

Reset Stack Pointer

Load

CLR

Clear

PUSH/POP

Push/Pop to/from the stack

INC/DEC

Increment/Decrement

TNZ

Test Negative or Zero

CPL, NEG

1 or 2 Complement

MUL

Byte Multiplication

SLL, SRL, SRA, RLC,
RRC

Shift and Rotate Operations

SWAP

Swap Nibbles

Immediate Instruction

Function

Load

Compare

BCP

Bit Compare

AND, OR, XOR

Logical Operations

ADC, ADD, SUB, SBC

Arithmetic Operations

ST72334J/N, ST72314J/N, ST72124J

101/148

ST7 ADDRESSING MODES (Cont'd)

14.1.6 Indirect Indexed (Short, Long)

This is a combination of indirect and short indexed
addressing modes. The operand is referenced by
its memory address, which is defined by the un-
signed addition of an index register value (X or Y)
with a pointer value located in memory. The point-
er address follows the opcode.

The indirect indexed addressing mode consists of
two sub-modes:

Indirect Indexed (Short)

The pointer address is a byte, the pointer size is a
byte, thus allowing 00 - 1FE addressing space,
and requires 1 byte after the opcode.

Indirect Indexed (Long)

The pointer address is a byte, the pointer size is a
word, thus allowing 64 Kbyte addressing space,
and requires 1 byte after the opcode.

Table

22.

Instructions

Supporting

Direct,

Indexed,

Indirect

and

Indirect

Indexed

Addressing Modes

14.1.7 Relative mode (Direct, Indirect)

This addressing mode is used to modify the PC
register value, by adding an 8-bit signed offset to
it.

The relative addressing mode consists of two sub-
modes:

Relative (Direct)

The offset follows the opcode.

Relative (Indirect)

The offset is defined in memory, of which the ad-
dress follows the opcode.

Lon g and Short

Instructions

Function

Load

Compare

AND, OR, XOR

Logical Operations

ADC, ADD, SUB, SBC

Arithmetic Addition/subtrac-
tion operations

BCP

Bit Compare

Short Instructions Only

Functio n

CLR

Clear

INC, DEC

Increment/Decrement

TNZ

Test Negative or Zero

CPL, NEG

1 or 2 Complement

BSET, BRES

Bit Operations

BTJT, BTJF

Bit Test and Jump Opera-
tions

SLL, SRL, SRA, RLC,
RRC

Shift and Rotate Operations

SWAP

Swap Nibbles

CALL, JP

Call or Jump subroutine

Available Relative Direct/

Indirect Instructions

Function

JRxx

Conditional Jump

CALLR

Call Relative

ST72334J/N, ST72314J/N, ST72124J

102/148

14.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set
consisting of 63 instructions. The instructions may

be subdivided into 13 main groups as illustrated in
the following table:

Using a pre-byte

The instructions are described with one to four
bytes.

In order to extend the number of available op-
codes for an 8-bit CPU (256 opcodes), three differ-
ent prebyte opcodes are defined. These prebytes
modify the meaning of the instruction they pre-
cede.

The whole instruction becomes:

PC-2

End of previous instruction

PC-1

Prebyte

opcode

PC+1

Additional word (0 to 2) according

to the number of bytes required to compute the ef-
fective address

These prebytes enable instruction in Y as well as
indirect addressing modes to be implemented.
They precede the opcode of the instruction in X or
the instruction using direct addressing mode. The
prebytes are:

PDY 90

Replace an X based instruction

using immediate, direct, indexed, or inherent ad-
dressing mode by a Y one.

PIX 92

Replace an instruction using di-

rect, direct bit, or direct relative addressing mode
to an instruction using the corresponding indirect
addressing mode.
It also changes an instruction using X indexed ad-
dressing mode to an instruction using indirect X in-
dexed addressing mode.

PIY 91

Replace an instruction using X in-

direct indexed addressing mode by a Y one.

Load and Transfer

CLR

Stack operation

PUSH

POP

RSP

Increment/Decrement

INC

DEC

Compare and Tests

TNZ

BCP

Logical operations

AND

XOR

CPL

NEG

Bit Operation

BSET

BRES

Conditional Bit Test and Branch

BTJT

BTJF

Arithmetic operations

ADC

ADD

SUB

SBC

MUL

Shift and Rotates

SLL

SRL

SRA

RLC

RRC

SWAP

SLA

Unconditional Jump or Call

JRA

JRT

JRF

CALL

CALLR

NOP

RET

Conditional Branch

JRxx

Interruption management

TRAP

WFI

HALT

IRET

Code Condition Flag modification

SIM

RIM

SCF

RCF

ST72334J/N, ST72314J/N, ST72124J

103/148

INSTRUCTION GROUPS (Cont'd)

Mnemo

Description

Fun ction/Example

Dst

Src

ADC

Add with Carry

A = A + M + C

ADD

Addition

A = A + M

AND

Logical And

A = A . M

BCP

Bit compare A, Memory

tst (A . M)

BRES

Bit Reset

bres Byte, #3

BSET

Bit Set

bset Byte, #3

BTJF

Jump if bit is false (0)

btjf Byte, #3, Jmp1

BTJT

Jump if bit is true (1)

btjt Byte, #3, Jmp1

CALL

Call subroutine

CALLR

Call subroutine relative

CLR

Clear

reg, M

Arithmetic Compare

tst(Reg - M)

reg

CPL

One Complement

A = FFH-A

reg, M

DEC

Decrement

dec Y

reg, M

HALT

Halt

IRET

Interrupt routine return

Pop CC, A, X, PC

INC

Increment

inc X

reg, M

Absolute Jump

jp [TBL.w]

JRA

Jump relative always

JRT

Jump relative

JRF

Never jump

jrf *

JRIH

Jump if ext. interrupt = 1

JRIL

Jump if ext. interrupt = 0

JRH

Jump if H = 1

H = 1 ?

JRNH

Jump if H = 0

H = 0 ?

JRM

Jump if I = 1

I = 1 ?

JRNM

Jump if I = 0

I = 0 ?

JRMI

Jump if N = 1 (minus)

N = 1 ?

JRPL

Jump if N = 0 (plus)

N = 0 ?

JREQ

Jump if Z = 1 (equal)

Z = 1 ?

JRNE

Jump if Z = 0 (not equal)

Z = 0 ?

JRC

Jump if C = 1

C = 1 ?

JRNC

Jump if C = 0

C = 0 ?

JRULT

Jump if C = 1

Unsigned <

JRUGE

Jump if C = 0

Jmp if unsigned >=

JRUGT

Jump if (C + Z = 0)

Unsigned >

ST72334J/N, ST72314J/N, ST72124J

104/148

INSTRUCTION GROUPS (Cont'd)

Mnemo

Description

Fun ction/Example

Dst

Src

JRULE

Jump if (C + Z = 1)

Unsigned <=

Load

dst <= src

reg, M

M, reg

MUL

Multiply

X,A = X * A

A, X, Y

X, Y, A

NEG

Negate (2's compl)

neg $10

reg, M

NOP

No Operation

OR operation

A = A + M

POP

Pop from the Stack

pop reg

reg

pop CC

PUSH

Push onto the Stack

push Y

reg, CC

RCF

Reset carry flag

C = 0

RET

Subroutine Return

RIM

Enable Interrupts

I = 0

RLC

Rotate left true C

C <= Dst <= C

reg, M

RRC

Rotate right true C

C => Dst => C

reg, M

RSP

Reset Stack Pointer

S = Max allowed

SBC

Subtract with Carry

A = A - M - C

SCF

Set carry flag

C = 1

SIM

Disable Interrupts

I = 1

SLA

Shift left Arithmetic

C <= Dst <= 0

reg, M

SLL

Shift left Logic

C <= Dst <= 0

reg, M

SRL

Shift right Logic

0 => Dst => C

reg, M

SRA

Shift right Arithmetic

Dst7 => Dst => C

reg, M

SUB

Subtraction

A = A - M

SWAP

SWAP nibbles

Dst[7..4] <=> Dst[3..0] reg, M

TNZ

Test for Neg & Zero

tnz lbl1

TRAP

S/W trap

S/W interrupt

WFI

Wait for Interrupt

XOR

Exclusive OR

A = A XOR M

ST72334J/N, ST72314J/N, ST72124J

105/148

15 ELECTRICAL CHARACTERISTICS

15.1 PARAMETER CONDITIONS

Unless otherwise specified, all voltages are re-
ferred to V

15.1.1 Minimum and Maximum values

Unless otherwise specified the minimum and max-
imum values are guaranteed in the worst condi-
tions of ambient temperature, supply voltage and
frequencies by tests in production on 100% of the
devices with an ambient temperature at T

=25

and T

max (given by the selected temperature

range).

Data based on characterization results, design
simulation and/or technology characteristics are
indicated in the table footnotes and are not tested
in production. Based on characterization, the min-
imum and maximum values refer to sample tests
and represent the mean value plus or minus three
times the standard deviation (mean

15.1.2 Typical values

Unless otherwise specified, typical data are based
on T

=25

C, V

=5V (for the 4.5V

5.5V

voltage range) and V

=3.3V (for the 3V

voltage range). They are given only as design
guidelines and are not tested.

15.1.3 Typical curves

Unless otherwise specified, all typical curves are
given only as design guidelines and are not tested.

15.1.4 Loading capacitor

The loading conditions used for pin parameter
measurement are shown in Figure 53.

Figure 53. Pin loading conditions

15.1.5 Pin input voltage

The input voltage measurement on a pin of the de-
vice is described in Figure 54.

Figure 54. Pin input voltage

ST7 PIN

ST72334J/N, ST72314J/N, ST72124J

106/148

15.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as "absolute maxi-
mum ratings" may cause permanent damage to
the device. This is a stress rating only and func-
tional operation of the device under these condi-

tions is not implied. Exposure to maximum rating
conditions for extended periods may affect device
reliability.

15.2.1 Voltage Characteristics

15.2.2 Current Characteristics

15.2.3 Thermal Characteristics

Notes:
1. Directly connecting the RESET and I/O pins to V

or V

could damage the device if an unintentional internal reset

is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter).
To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7k

for

RESET, 10k

for I/Os). Unused I/O pins must be tied in the same way to V

or V

according to their reset configuration.

2. When the current limitation is not possible, the V

absolute maximum rating must be respected, otherwise refer to

INJ(PIN)

specification. A positive injection is induced by V

while a negative injection is induced by V

3. All power (V

) and ground (V

) lines must always be connected to the external supply.

4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout
the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken:
- Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage
is lower than the specified limits)
- Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as
far as possible from the analog input pins.
5. When several inputs are submitted to a current injection, the maximum

INJ(PIN)

is the absolute sum of the positive

and negative injected currents (instantaneous values). These results are based on characterisation with

INJ(PIN)

maxi-

mum current injection on four I/O port pins of the device.
6. True open drain I/O port pins do not accept positive injection.

Symbol

Ratings

Maximum value

Unit

- V

Supply voltage

6.5

Input voltage on any pin

1) & 2)

-0.3 to V

+0.3

DDx

| and |

SSx

Variations between different digital power pins

SSA

- V

SSx

Variations between digital and analog ground pins

ESD(HBM)

Electro-static discharge voltage (Human Body Model)

see Section 15.7.2 "Absolute Electri-
cal Sensitivity" on page 121

ESD(MM)

Electro-static discharge voltage (Machine Model)

Symbol

Ratings

Maximum value

Unit

VDD

Total current into V

power lines (source)

150

VSS

Total current out of V

ground lines (sink)

150

Output current sunk by any standard I/O and control pin

Output current sunk by any high sink I/O pin

Output current source by any I/Os and control pin

- 25

INJ(PIN)

2) & 4)

Injected current on ISPSEL pin

Injected current on RESET pin

Injected current on OSC1 and OSC2 pins

Injected current on any other pin

5) & 6)

INJ(PIN)

Total injected current (sum of all I/O and control pins)

Symbol

Ratings

Value

Unit

STG

Storage temperature range

-65 to +150

Maximum junction temperature (see Section 17 "DEVICE CONFIGURATION AND ORDER-
ING INFORMATION" on page 143 )

ST72334J/N, ST72314J/N, ST72124J

107/148

15.3 OPERATING CONDITIONS

15.3.1 General Operating Conditions

Figure 55. f

OSC

Maximum Operating Frequency Versus V

Supply Voltage for ROM devices

Figure 56. f

OSC

Maximum Operating Frequency Versus V

Supply Voltage for FLASH devices

Notes:
1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T

=-40 to +125

3. FLASH programming tested in production at maximum T

with two different conditions: V

=5.5V, f

CPU

=6MHz and

=3.2V, f

CPU

=4MHz.

Symbol

Parameter

Condi tions

Min

Max

Unit

Supply voltage

see Figure 55 and Figure 56

3.2

5.5

OSC

External clock frequency

3.5V for ROM devices

4.5V for FLASH devices

MHz

3.2V

Ambient temperature range

1 Suffix Version

6 Suffix Version

-40

7 Suffix Version

-40

105

3 Suffix Version

-40

125

OSC

[MHz]

SUPPLY VOLTAGE [V]

1
0

2.5

3.2

3.5

4.5

5.5

FUNCTIONALI TY

FUNCTI ONALITY

FUNCTIONALI TY
GUARANTEE D
IN THIS AREA

NOT GUARAN TEED

IN THIS AREA

NOT GUARANTEED
IN THIS AREA
WITH RESONA TOR

NOT GUARANTEED

IN THIS AREA AT T

> 85

OSC

[MHz]

SUPPLY VOLTAGE [V]

1
0

2.5

3.2

3.5

4.5

5.5

FUNCTIONALI TY

FUNCT IONALITY

FUNCTIONALI TY
GUARANTEE D
IN THIS AREA

NOT GUARAN TEED

IN THIS AREA

NOT GUARANTEE D
IN THIS AREA
WITH RESONATO R

3.85

FUNCT IONALIT Y

ST72334J/N, ST72314J/N, ST72124J

108/148

OPERATING CONDITIONS (Cont'd)

15.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for V

, f

OSC

, and T

Figure 57. High LVD Threshold Versus V

and f

OSC

for FLASH devices

Figure 58. Medium LVD Threshold Versus V

and f

OSC

for FLASH devices

Figure 59. Low LVD Threshold Versus V

and f

OSC

for FLASH devices

2)4)

Notes:
1. LVD typical data are based on T

=25

C. They are given only as design guidelines and are not tested.

2. Data based on characterization results, not tested in production.
3. The V

rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production.

4.If the low LVD threshold is selected, when V

falls below 3.2V, (V

minimum operating voltage), the device is guar-

anteed to continue functioning until it goes into reset state. The specified V

min. value is necessary in the device power

on phase, but during a power down phase or voltage drop the device will function below this min. level.

Symbol

Parameter

Condition s

Min

Typ

Max

Unit

IT+

Reset release threshold (V

rise)

High Threshold
Med. Threshold
Low Threshold

4.10

3.75

3.25

4.30
3.90
3.35

4.50
4.05
3.45

IT-

Reset generation threshold (V

fall)

High Threshold
Med. Threshold
Low Threshold

3.85
3.50
3.00

4.05
3.65
3.10

4.25
3.80
3.20

hys

LVD voltage threshold hysteresis

IT+

-V

IT-

200

250

300

POR

rise time rate

0.2

V/ms

g(VDD)

Filtered glitch delay on V

Not detected by the LVD

OSC

[MHz]

SUPPLY VOLTAGE [V]

2.5

3.5

4.5

5.5

FUNCTI ONAL AREA

DEVICE UNDER

FUNCT IONALITY AND RESE T NOT GUARANTEED IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85

RESET

IN THIS AREA

FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA

IT-

3.85

OSC

[MHz]

SUPPLY VOLTAGE [V]

2.5

IT-

3.5V

4.5

5.5

FUNCTI ONAL AREA

DEVICE UNDER

FUNCTIONALI TY AND RESET NOT GUARANTEE D IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85

RESET

IN THIS AREA

FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA

OSC

[MHz]

SUPPLY VOLTAGE [V]

2.5

IT-

3.5

4.5

5.5

FUNCTI ONAL AREA

DEVICE UNDER

FUNCTIONA LITY NOT GUARAN TEED IN THIS AREA

FOR TEMPERATURES HIGHER THAN 85

RESET

IN THIS AREA

FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA

3.2

SEE NOTE 4

ST72334J/N, ST72314J/N, ST72124J

109/148

FUNCTIONAL OPERATING CONDITIONS (Cont'd)

Figure 60. High LVD Threshold Versus V

and f

OSC

for ROM devices

Figure 61. Medium LVD Threshold Versus V

and f

OSC

for ROM devices

Figure 62. Low LVD Threshold Versus V

and f

OSC

for ROM devices

2)3)

Notes:
1. LVD typical data are based on T

=25

C. They are given only as design guidelines and are not tested.

2. The minimum V

rise time rate is needed to insure a correct device power-on and LVD reset. Not tested in production.

3. If the low LVD threshold is selected, when V

falls below 3.2V, (V

minimum operating voltage), the device is guar-

anteed to continue functioning until it goes into reset state. The specified V

min. value is necessary in the device power

on phase, but during a power down phase or voltage drop the device will function below this min. level.

OSC

[MHz]

SUPPLY VOLTAGE [V]

2.5

3.5

4.5

5.5

FUNCTI ONAL AREA

DEVICE UNDER

RESET

IN THIS AREA

FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA

IT-

3.85

OSC

[MHz]

SUPPLY VOLTAGE [V]

2.5

IT-

3.5V

4.5

5.5

FUNCTI ONAL AREA

DEVICE UNDER

RESET

IN THIS AREA

FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA

OSC

[MHz]

SUPPLY VOLTAGE [V]

2.5

IT-

3.00V

3.5

4.5

5.5

FUNCTI ONAL AREA

DEVICE UNDER

RESET

IN THIS AREA

FUNCTI ONALITY
NOT GUARAN TEED
IN THIS AREA

ST72334J/N, ST72314J/N, ST72124J

110/148

15.4 SUPPLY CURRENT CHARACTERISTICS

The following current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock
source current consumption. To get the total de-

vice consumption, the two current values must be
added (except for HALT mode for which the clock
is stopped).

15.4.1 RUN and SLOW Modes

Figure 63. Typical I

in RUN vs. f

CPU

Figure 64. Typical I

in SLOW vs. f

CPU

Notes:
1. Typical data are based on T

=25

C, V

=5V (4.5V

5.5V range) and V

=3.4V (3.2V

3.6V range).

2. Data based on characterization results, tested in production at V

max. and f

CPU

max.

3. CPU running with memory access, all I/O pins in input mode with a static value at V

or V

(no load), all peripherals

in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.
4. SLOW mode selected with f

CPU

based on f

OSC

divided by 32. All I/O pins in input mode with a static value at V

(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

Symbol

Parameter

Conditions

Max

Unit

DD(

Ta)

Supply current variation vs. temperature

Constant V

and f

CPU

Symbol

Parameter

Conditions

Typ

Max

Unit

Supply current in RUN mode

(see Figure 63)

4.5V

5.5V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

1.2
2.1
3.9
7.4

1.8
3.5
7.0

14.0

Supply current in SLOW mode

(see Figure 64)

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.4
0.5
0.7
1.0

0.9
1.1
1.4
2.0

Supply current in RUN mode

(see Figure 63)

3.2V

3.6V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

0.3
0.8
1.6
3.5

1.5

3
7

Supply current in SLOW mode

(see Figure 64)

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.1
0.2
0.3
0.5

0.3
0.5
0.6
1.0

3.2

3.5

4.5

5.5

VDD [V]

IDD [mA]

8MHz

4MHz

2MHz

1MHz

3.2

3.5

4.5

5.5

VDD [V]

0.2

0.4

0.6

0.8

1.2

IDD [mA]

500kHz

250kHz

125kHz

62.5kHz

ST72334J/N, ST72314J/N, ST72124J

111/148

SUPPLY CURRENT CHARACTERISTICS (Cont'd)

15.4.2 WAIT and SLOW WAIT Modes

Figure 65. Typical I

in WAIT vs. f

CPU

Figure 66. Typical I

in SLOW-WAIT vs. f

CPU

Notes:
1. Typical data are based on T

=25

C, V

=5V (4.5V

5.5V range) and V

=3.4V (3.2V

3.6V range).

2. Data based on characterization results, tested in production at V

max. and f

CPU

max.

3. All I/O pins in input mode with a static value at V

or V

(no load), all peripherals in reset state; clock input (OSC1)

driven by external square wave, CSS and LVD disabled.
4. SLOW-WAIT mode selected with f

CPU

based on f

OSC

divided by 32. All I/O pins in input mode with a static value at

or V

(no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD

disabled.

Symbol

Parameter

Conditions

Typ

Max

Unit

Supply current in WAIT mode

(see Figure 65)

4.5V

5.5V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

0.35

0.7
1.3
2.5

0.6
1.2
2.1
4.0

Supply current in SLOW WAIT mode

(see Figure 66)

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

0.05

0.1
0.2
0.5

0.1
0.2
0.4
1.0

Supply current in WAIT mode

(see Figure 65)

3.2V

3.6V

OSC

=2MHz, f

CPU

=1MHz

OSC

=4MHz, f

CPU

=2MHz

OSC

=8MHz, f

CPU

=4MHz

OSC

=16MHz, f

CPU

=8MHz

150
300
500

100
300
600

1000

Supply current in SLOW WAIT mode

(see Figure 66)

OSC

=2MHz, f

CPU

=62.5kHz

OSC

=4MHz, f

CPU

=125kHz

OSC

=8MHz, f

CPU

=250kHz

OSC

=16MHz, f

CPU

=500kHz

40
80

120

100
160
250

3.2

3.5

4.5

5.5

VDD [V]

0.5

1.5

2.5

IDD [mA]

8MHz

4MHz

2MHz

1MHz

3.2

3.5

4.5

5.5

VDD [V]

0.05

0.1

0.15

0.2

0.25

0.3

0.35

IDD [mA]

500kHz

250kHz

125kHz

62.5kHz

ST72334J/N, ST72314J/N, ST72124J

112/148

SUPPLY CURRENT CHARACTERISTICS (Cont'd)

15.4.3 HALT and ACTIVE-HALT Modes

15.4.4 Supply and Clock Managers

The previous current consumption specified for
the ST7 functional operating modes over tempera-
ture range does not take into account the clock

source current consumption. To get the total de-
vice consumption, the two current values must be
added (except for HALT mode).

15.4.5 On-Chip Peripherals

Notes:
1. Typical data are based on T

=25

2. All I/O pins in input mode with a static value at V

or V

(no load), CSS and LVD disabled. Data based on charac-

terization results, tested in production at V

max. and f

CPU

max.

3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode
with a static value at V

or V

(no load); clock input (OSC1) driven by external square wave, LVD disabled.

4. Data based on characterization results, not tested in production.
5. Data based on characterization results done with the external components specified in Section 15.5.3 and Section
15.5.5, not tested in production.
6. As the oscillator is based on a current source, the consumption does not depend on the voltage.
7. Data based on a differential I

measurement between reset configuration (timer counter running at f

CPU

/4) and timer

counter stopped (selecting external clock capability). Data valid for one timer.
8. Data based on a differential I

measurement between reset configuration and a permanent SPI master communica-

tion (data sent equal to 55h).
9. Data based on a differential I

measurement between reset configuration and continuous A/D conversions.

Symbol

Parameter

Condition s

Typ

Max

Unit

Supply current in HALT mode

=5.5V

-40

+85

-40

+125

=3.6V

-40

+85

-40

+125

Supply current in ACTIVE-HALT mode

150

Symbol

Parameter

Condit ions

Typ

Max

Unit

DD(CK)

Supply current of internal RC oscillator

500

750

Supply current of external RC oscillator

525

750

Supply current of resonator oscillator

5) & 6)

LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator

200
300
450
700

400
550
750

1000

Clock security system supply current

150

350

DD(LVD)

LVD supply current

HALT mode

100

150

Symbol

Parameter

Conditions

Typ

Unit

DD(TIM)

16-bit Timer supply current

CPU

=8MHz

3.4V

5.0V

150

DD(SPI)

SPI supply current

CPU

=8MHz

3.4V

250

5.0V

350

DD(ADC)

ADC supply current when converting

ADC

=4MHz

3.4V

800

5.0V

1100

ST72334J/N, ST72314J/N, ST72124J

113/148

15.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

15.5.1 General Timings

15.5.2 External Clock Source

Figure 67. Typical Application with an External Clock Source

Notes:
1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch.

c(INST)

is the number of t

CPU

cycles needed to finish

the current instruction execution.
3. Data based on design simulation and/or technology characteristics, not tested in production.

Symbol

Parameter

Conditi ons

Min

Typ

Max

Unit

c(INST)

Instruction cycle time

CPU

=8MHz

250

375

1500

v(IT)

Interrupt reaction time

v(IT)

c(INST)

+ 10

CPU

=8MHz

1.25

2.75

Symbol

Parameter

Condi tions

Min

Typ

Max

Unit

OSC1H

OSC1 input pin high level voltage

see Figure 67

0.7xV

OSC1L

OSC1 input pin low level voltage

0.3xV

w(OSC1H)

w(OSC1L)

OSC1 high or low time

r(OSC1)

f(OSC1)

OSC1 rise or fall time

OSCx Input leakage current

OSC1

OSC2

OSC

EXTERNAL

ST72XXX

CLOCK SOURCE

Not connected internally

OSC1L

OSC1H

r(OSC1)

f(OSC1)

w(OSC1H)

w(OSC1L)

90%

10%

ST72334J/N, ST72314J/N, ST72124J

114/148

CLOCK AND TIMING CHARACTERISTICS (Cont'd)

15.5.3 Crystal and Ceramic Resonator Oscillators

The ST7 internal clock can be supplied with four
different Crystal/Ceramic resonator oscillators. All
the information given in this paragraph are based
on characterization results with specified typical
external componants. In the application, the reso-
nator and the load capacitors have to be placed as

close as possible to the oscillator pins in order to
minimize output distortion and start-up stabiliza-
tion time. Refer to the crystal/ceramic resonator
manufacturer for more details (frequency, pack-
age, accuracy...).

15.5.3.1 Typical Crystal Resonators

Figure 68. Application with a Crystal Resonator

Notes:
1. Resonator characteristics given by the crystal manufacturer.
2. t

SU(OSC)

is the typical oscillator start-up time measured between V

=2.8V and the fetch of the first instruction (with a

quick V

ramp-up from 0 to 5V (<50

s).

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value.

Refer to crystal manufacturer for more details.

Symbol

Parameter

Conditio ns

Min

Max

Unit

OSC

Oscillator Frequency

LP: Low power oscillator
MP: Medium power oscillator
MS: Medium speed oscillator
HS: High speed oscillator

>2
>4
>8

2
4
8

MHz

Feedback resistor

Recommanded load capacitances ver-
sus equivalent serial resistance of the
crystal or ceramic resonator (R

)

=200

LP oscillator

=200

MP oscillator

=200

MS oscillator

=100

HS oscillator

38
32
18
15

56
46
26
21

OSC2 driving current

=5V

LP oscillator

MP oscillator
MS oscillator
HS oscillator

110
180
400

100
190
360
700

Opti on

Byte

Config.

Reference

Freq.

Characteristic

[pF]

SU(osc)

[ms]

JAUCH

S-200-30-30/50

2MHz

OSC

30ppm

]

, Typ. R

=200

10~15

SS3-400-30-30/30

4MHz

OSC

30ppm

]

, Typ. R

=60

7~10

SS3-800-30-30/30

8MHz

OSC

30ppm

]

, Typ. R

=25

2.5~3

SS3-1600-30-30/30

16MHz

OSC

30ppm

]

, Typ. R

=15

1~1.5

OSC2

OSC1

OSC

ST72XXX

RESONATOR

ST72334J/N, ST72314J/N, ST72124J

115/148

CLOCK AND TIMING CHARACTERISTICS (Cont'd)

15.5.4 Typical Ceramic Resonators

Note:
t

SU(OSC)

is the typical oscillator start-up time measured between V

=2.8V and the fetch of the first instruction (with a

quick V

ramp-up from 0 to 5V (<50

s).

Figure 69. Application with Ceramic Resonator

Notes:
1. Resonator characteristics given by the ceramic resonator manufacturer.
2. t

SU(OSC)

is the typical oscillator start-up time measured between V

=2.8V and the fetch of the first instruction (with a

quick V

ramp-up from 0 to 5V (<50

s).

3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small R

value.

Refer to Table 23 and Table 24 and to the ceramic resonator manufacturer's documentation for more details.

Symbol

Parameter

Conditions

Typ

Unit

SU(osc)

Ceramic resonator startup time

2MHz

4.2

4MHz

2.1

8MHz

1.1

16MHz

0.7

OSC2

OSC1

OSC

ST72XXX

RESONATOR

WHEN RESONATOR WITH
INTEGRATE D CAPACI TORS

F(EXT)

ST72334J/N, ST72314J/N, ST72124J

116/148

CLOCK AND TIMING CHARACTERISTICS (Cont'd)

Table 23. Typical Ceramic Resonators

Table 24. Resonator Frequency Correlation Factor

Notes:
1. Murata Ceralock
2. V

4.5 to 5.5V

3. Values in parentheses refer to the capacitors integrated in the resonator

Option Byte

Config.

OSC

(MHz)

Resonator Part Number

[pF]

FEXT

]

CSB1000JA

100

Open

3.3

CSBF1000JA

CSTS0200MGA06

(47)

CSTCC2.00MGA0H6

CSTS0200MGA06

CSTCC2.00MGA0H6

CSTS0400MGA06

CSTCC4.00MGA0H6

CSTS0400MGA06

CSTCC4.00MGA0H6

CSTS0800MGA06

CSTCC8.00MGA0H6

CSTS0800MGA06

CSTCC8.00MGA0H6

CST10.0MTWA

CSTCC10.0MGA

(15)

CST12.0MTWA

CSTCS12.0MTA

(30)

CSA16.00MXZA040

CST16.00MXWA0C3

(15)

CSACV16.00MXA040Q

CSTCV16.00MXA0H3Q

(15)

Option
Byte
Config.

Resonator

Corre-
lation
%

Refer-
ence IC

Option
Byte
Config.

Resonator

Corre-
lation
%

Refer-
ence IC

CSB1000JA

+0.03

4069UBE

CSTS0400MGA06

-0.03

74HCU04

CSTS0200MGA06

-0.20

74HCU04

CSTCC4.00MGA0H6

-0.05

CSTCC2.00MGA0H6

-0.16

CSTS0800MGA06

+0.03

CSTS0200MGA06

-0.21

CSTCC4.00MGA0H6

+0.02

CSTCC2.00MGA0H6

-0.19

CSTS0800MGA06

+0.02

CSTS0400MGA06

0.02

CSTCC8.00MGA0H6

+0.01

CSTCC4.00MGA0H6

-0.05

CSTS10.0MTWA

+0.38

4069UBE

CSTCC10.0MGA

+0.61

CST12.0MTWA

+0.38

CSTCS12.0MTA

+0.42

CSA16.00MXZA040

+0.10

74HCU04

CSACV16.00MXA040Q +0.08

ST72334J/N, ST72314J/N, ST72124J

117/148

CLOCK CHARACTERISTICS (Cont'd)

15.5.5 RC Oscillators

The ST7 internal clock can be supplied with an RC
oscillator. This oscillator can be used with internal

or external components (selectable by option
byte).

Figure 70. Typical Application with RC oscillator

Figure 71. Typical Internal RC Oscillator

Figure 72. Typical External RC Oscillator

Notes:
1. Data based on characterization results.
2. Guaranteed frequency range with the specified C

and R

ranges taking into account the device process variation.

Data based on design simulation.
3. Data based on characterization results done with V

nominal at 5V, not tested in production.

4. R

must have a positive temperature coefficient (ppm/

C), carbon resistors should therefore not be used.

5. Important: when no external C

is applied, the capacitance to be considered is the global parasitic capacitance which

is subject to high variation (package, application...). In this case, the RC oscillator frequency tuning has to be done by
trying out several resistor values.

Symbol

Parameter

Conditi ons

Min

Typ

Max

Unit

OSC

Internal RC oscillator frequency

see Figure 71

3.60

5.10

MHz

External RC oscillator frequency

SU(OSC)

Internal RC Oscillator Start-up Time

2.0

External RC Oscillator Start-up Time

=47K

="0"pF

=47K

=100pF

=10K

=6.8pF

=10K

=470pF

1.0
6.5
0.7
3.0

Oscillator external resistor

see Figure 72

Oscillator external capacitor

470

OSC1

OSC2

OSC

EXTERN AL RC

INTERNAL RC

REF

Current copy

Voltage generator

discharge

ST72XXX

3.2

5.5

VDD [V]

3.8

3.9

4.1

4.2

4.3

fosc [MHz]

-40

+25

+85

+125

6.8

100

270

470

Cex [pF]

fosc [MHz]

Rex=10KOhm

Rex=15KOhm

Rex=22KOhm

Rex=33KOhm

Rex=39KOhm

Rex=47KOhm

ST72334J/N, ST72314J/N, ST72124J

119/148

15.6 MEMORY CHARACTERISTICS

15.6.1 RAM and Hardware Registers

15.6.2 EEPROM Data Memory

15.6.3 FLASH Program Memory

Notes:
1. Minimum V

supply voltage without losing data stored in RAM (in in HALT mode or under RESET) or in hardware

registers (only in HALT mode). Guaranteed by construction, not tested in production.
2. Data based on characterization results, tested in production at T

=25

3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device)
4. The data retention time increases when the T

decreases.

5. Data based on reliability test results and monitored in production.

Symbol

Parameter

Conditi ons

Min

Typ

Max

Unit

Data retention mode

HALT mode (or RESET)

1.6

Symbol

Parameter

Conditi ons

Min

Typ

Max

Unit

prog

Programming time for 1~16 bytes

-40

+85

-40

+125

ret

Data retention

+55

Years

Write erase cycles

+25

300 000

Cycles

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

A(prog)

Programming temperature range

prog

Programming time for 1~16 bytes

+25

Programming time for 4 or 8kBytes

+25

2.1

6.4

sec

ret

Data retention

=+55

years

Write erase cycles

+25

100

cycles

ST72334J/N, ST72314J/N, ST72124J

120/148

15.7 EMC CHARACTERISTICS

Susceptibility tests are performed on a sample ba-
sis during product characterization.

15.7.1 Functional EMS

(Electro Magnetic Susceptibility)

Based on a simple running application on the
product (toggling 2 LEDs through I/O ports), the
product is stressed by two electro magnetic events
until a failure occurs (indicated by the LEDs).

ESD: Electro-Static Discharge (positive and
negative) is applied on all pins of the device until
a functional disturbance occurs. This test
conforms with the IEC 1000-4-2 standard.

FTB: A Burst of Fast Transient voltage (positive
and negative) is applied to V

and V

through

a 100pF capacitor, until a functional disturbance
occurs. This test conforms with the IEC 1000-4-
4 standard.

A device reset allows normal operations to be re-
sumed.

Figure 74. EMC Recommended star network power supply connection

Notes:
1. Data based on characterization results, not tested in production.
2. The suggested 10nF and 0.1

F decoupling capacitors on the power supply lines are proposed as a good price vs. EMC

performance tradeoff. They have to be put as close as possible to the device power supply pins. Other EMC recommen-
dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

Symbol

Parameter

Condition s

Neg

Pos

Unit

FESD

Voltage limits to be applied on any I/O pin
to induce a functional disturbance

5V, T

+25

C, f

OSC

8MHz

conforms to IEC 1000-4-2

-1

FFTB

Fast transient voltage burst limits to be ap-
plied through 100pF on V

and V

pins

to induce a functional disturbance

5V, T

+25

C, f

OSC

8MHz

conforms to IEC 1000-4-4

-4

0.1

10nF

ST72XXX

SSA

DDA

0.1

POWER
SUPPLY
SOURCE

ST7
DIGITAL NOISE
FILTERING

EXTERNAL
NOISE
FILTERING

ST72334J/N, ST72314J/N, ST72124J

121/148

EMC CHARACTERISTICS (Cont'd)

15.7.2 Absolute Electrical Sensitivity

Based on three different tests (ESD, LU and DLU)
using specific measurement methods, the product
is stressed in order to determine its performance in
terms of electrical sensitivity. For more details, re-
fer to the AN1181 ST7 application note.

15.7.2.1 Electro-Static Discharge (ESD)

Electro-Static Discharges (3 positive then 3 nega-
tive pulses separated by 1 second) are applied to
the pins of each sample according to each pin
combination. The sample size depends of the
number of supply pins of the device (3 parts*(n+1)
supply pin). Two models are usually simulated:
Human Body Model and Machine Model. This test
conforms to the JESD22-A114A/A115A standard.
See Figure 75 and the following test sequences.

Human Body Model Test Sequence

is loaded through S1 by the HV pulse gener-

ator.

S1 switches position from generator to R.

A discharge from C

through R (body resistance)

to the ST7 occurs.

S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.

Machine Model Test Sequence

is loaded through S1 by the HV pulse gener-

ator.

S1 switches position from generator to ST7.

A discharge from C

to the ST7 occurs.

S2 must be closed 10 to 100ms after the pulse

delivery period to ensure the ST7 is not left in
charge state. S2 must be opened at least 10ms
prior to the delivery of the next pulse.

R (machine resistance), in series with S2, en-

sures a slow discharge of the ST7.

Absolute Maximum Ratings

Figure 75. Typical Equivalent ESD Circuits

Notes:
1. Data based on characterization results, not tested in production.

Symbol

Ratings

Conditions

Maximum value

Unit

ESD(HBM)

Electro-static discharge voltage
(Human Body Model)

+25

3000

ESD(MM)

Electro-static discharge voltage
(Machine Model)

+25

TBD

ST7

R=1500

HIGH VOLTAGE

100pF

PULSE

GENERATOR

ST7

HIGH VOLTAGE

200pF

PULSE

GENERAT OR

R=10k~10M

HUMAN BODY MODEL

MACHINE MODEL

ST72334J/N, ST72314J/N, ST72124J

122/148

EMC CHARACTERISTICS (Cont'd)

15.7.2.2 Static and Dynamic Latch-Up

LU: 3 complementary static tests are required
on 10 parts to assess the latch-up performance.
A supply overvoltage (applied to each power
supply pin), a current injection (applied to each
input, output and configurable I/O pin) and a
power supply switch sequence are performed
on each sample. This test conforms to the EIA/
JESD 78 IC latch-up standard. For more details,
refer to the AN1181 ST7 application note.

DLU: Electro-Static Discharges (one positive
then one negative test) are applied to each pin
of 3 samples when the micro is running to
assess the latch-up performance in dynamic
mode. Power supplies are set to the typical
values, the oscillator is connected as near as
possible to the pins of the micro and the
component is put in reset mode. This test
conforms to the IEC1000-4-2 and SAEJ1752/3
standards and is described in Figure 76. For
more

details,

refer

the

AN1181

ST7

application note.

Electrical Sensitivities

Figure 76. Simplified Diagram of the ESD Generator for DLU

Notes:
1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-
ifications, that means when a device belongs to Class A it exceeds the JEDEC standard. B Class strictly covers all the
JEDEC criteria (international standard).
2. Schaffner NSG435 with a pointed test finger.

Symbol

Parameter

Conditions

Class

Static latch-up class

+25

+85

TBD
TBD

DLU

Dynamic latch-up class

5.5V, f

OSC

4MHz, T

+25

=50M

=330

150pF

ESD

HV RELAY

DISCHAR GE TIP

DISCHARGE
RETURN CONNECTION

GENERATOR

ST7

ST72334J/N, ST72314J/N, ST72124J

123/148

EMC CHARACTERISTICS (Cont'd)

15.7.3 ESD Pin Protection Strategy

To protect an integrated circuit against Electro-
Static Discharge the stress must be controlled to
prevent degradation or destruction of the circuit el-
ements. The stress generally affects the circuit el-
ements which are connected to the pads but can
also affect the internal devices when the supply
pads receive the stress. The elements to be pro-
tected must not receive excessive current, voltage
or heating within their structure.

An ESD network combines the different input and
output ESD protections. This network works, by al-
lowing safe discharge paths for the pins subjected
to ESD stress. Two critical ESD stress cases are
presented in Figure 77 and Figure 78 for standard
pins and in Figure 79 and Figure 80 for true open
drain pins.

Standard Pin Protection

To protect the output structure the following ele-
ments are added:

A diode to V

(3a) and a diode from V

(3b)

A protection device between V

and V

(4)

To protect the input structure the following ele-
ments are added:

A resistor in series with the pad (1)
A diode to V

(2a) and a diode from V

(2b)

A protection device between V

and V

(4)

Figure 77. Positive Stress on a Standard Pad vs. V

Figure 78. Negative Stress on a Standard Pad vs. V

(1)

(2a)

(2b)

(4)

OUT

(3a)

(3b)

Main path

Path to avoid

(1)

(2a)

(2b)

(4)

OUT

(3a)

(3b)

Main path

ST72334J/N, ST72314J/N, ST72124J

124/148

EMC CHARACTERISTICS (Cont'd)

True Open Drain Pin Protection

The centralized protection (4) is not involved in the
discharge of the ESD stresses applied to true
open drain pads due to the fact that a P-Buffer and
diode to V

are not implemented. An additional

local protection between the pad and V

(5a &

5b) is implemented to completly absorb the posi-
tive ESD discharge.

Multisupply Configuration

When several types of ground (V

, V

SSA

, ...) and

power supply (V

, V

DDA

, ...) are available for any

reason (better noise immunity...), the structure
shown in Figure 81 is implemented to protect the
device against ESD.

Figure 79. Positive Stress on a True Open Drain Pad vs. V

Figure 80. Negative Stress on a True Open Drain Pad vs. V

Figure 81. Multisupply Configuration

(1)

(2b)

(4)

OUT

(3b)

Main path

Path to avoid

(5a)

(5b)

(1)

(2b)

(4)

OUT

(3b)

Main path

(3b)

DDA

SSA

DDA

BACK TO BACK DIODE

BETWEEN GROUNDS

SSA

ST72334J/N, ST72314J/N, ST72124J

125/148

15.8 I/O PORT PIN CHARACTERISTICS

15.8.1 General Characteristics

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Figure 82. Two typical Applications with unused I/O Pin

Figure 83. Typical I

vs. V

with V

Notes:
1. Unless otherwise specified, typical data are based on T

=25

C and V

=5V.

2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for
example or an external pull-up or pull-down resistor (see Figure 82). Data based on design simulation and/or technology
characteristics, not tested in production.
5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

current characteristics de-

scribed in Figure 83). This data is based on characterization results, tested in production at V

max.

6. Data based on characterization results, not tested in production.
7. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external
interrupt source.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Input low level voltage

0.3xV

Input high level voltage

0.7xV

hys

Schmitt trigger voltage hysteresis

400

Input leakage current

Static current consumption

Floating input mode

200

Weak pull-up equivalent resistor

=5V

120

250

=3.3V

170

200

300

I/O pin capacitance

f(IO)out

Output high to low level fall time

=50pF

Between 10% and 90%

r(IO)out

Output low to high level rise time

w(IT)in

External interrupt pulse time

CPU

10k

UNUSED I/O PORT

ST72XXX

10k

UNUSED I/O PORT

ST72XXX

3.2

3.5

4.5

5.5

Vdd [V]

Ipu [

Ta=-40

Ta=25

Ta=85

Ta=125

ST72334J/N, ST72314J/N, ST72124J

126/148

I/O PORT PIN CHARACTERISTICS (Cont'd)

15.8.2 Output Driving Current

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Figure 84. Typical V

at V

=5V (standard)

Figure 85. Typical V

at V

=5V (high-sink)

Figure 86. Typical V

-V

at V

=5V

Notes:
1. The I

current sunk must always respect the absolute maximum rating specified in Section 15.2.2 and the sum of I

(I/O ports and control pins) must not exceed I

VSS

2. The I

current sourced must always respect the absolute maximum rating specified in Section 15.2.2 and the sum of

(I/O ports and control pins) must not exceed I

VDD

. True open drain I/O pins does not have V

Symbol

Parameter

Conditions

Min

Max

Unit

Output low level voltage for a standard I/O pin
when 8 pins are sunk at same time
(see Figure 84 and Figure 87)

=5V

=+5mA

1.3

=+2mA

0.5
0.6

Output low level voltage for a high sink I/O pin
when 4 pins are sunk at same time
(see Figure 85 and Figure 88)

=+20mA, T

1.3
1.5

=+8mA

0.6
0.7

Output high level voltage for an I/O pin
when 4 pins are sourced at same time
(see Figure 86 and Figure 89)

=-5mA

-1.6

=-2mA

-0.8

Iio [mA]

0.5

1.5

2.5

Vol [V] at Vdd=5V

Ta=-40

Ta=25

Ta=85

Ta=125

Iio [mA]

0.5

1.5

Vol [V] at Vdd=5V

Ta=-40

Ta=25

Ta=85

Ta=125

-8

-6

-4

-2

Iio [mA]

Vdd-Voh [V] at Vdd=5V

Ta=-40

Ta=25

Ta=85

Ta=125

ST72334J/N, ST72314J/N, ST72124J

127/148

I/O PORT PIN CHARACTERISTICS (Cont'd)

Figure 87. Typical V

vs. V

(standard I/Os)

Figure 88. Typical V

vs. V

(high-sink I/Os)

Figure 89. Typical V

-V

vs. V

3.2

3.5

4.5

5.5

Vdd [V]

0.2

0.25

0.3

0.35

0.4

0.45

0.5

Vol [V] at Iio=2mA

Ta=-40

Ta=25

Ta=85

Ta=125

3.2

3.5

4.5

5.5

Vdd [V]

0.5

0.6

0.7

0.8

0.9

1.1

1.2

1.3

1.4

Vol [V] at Iio=5mA

Ta=-40

Ta=25

Ta=85

Ta=125

3.2

3.5

4.5

5.5

Vdd [V]

0.2

0.25

0.3

0.35

0.4

0.45

0.5

0.55

Vol [V] at Iio=8mA

Ta=-40

Ta=25

Ta=85

Ta=125

3.2

3.5

4.5

5.5

Vdd [V]

0.5

0.7

0.9

1.1

1.3

1.5

Vol [V] at Iio=20mA

Ta=-40

Ta=25

Ta=85

Ta=125

3.5

4.5

5.5

Vdd [V]

Vdd-Voh [V] at Iio=-5mA

Ta=-40

Ta=25

Ta=85

Ta=125

3.2

3.5

4.5

5.5

Vdd [V]

2.5

3.5

4.5

5.5

Vdd-Voh [V] at Iio=-2mA

Ta=-40

Ta=25

Ta=85

Ta=125

ST72334J/N, ST72314J/N, ST72124J

128/148

15.9 CONTROL PIN CHARACTERISTICS

15.9.1 Asynchronous RESET Pin

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Figure 90. Typical Application with RESET pin

Notes:
1. Unless otherwise specified, typical data are based on T

=25

C and V

=5V.

2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The I

current sunk must always respect the absolute maximum rating specified in Section 15.2.2 and the sum of I

(I/O ports and control pins) must not exceed I

VSS

5. The R

pull-up equivalent resistor is based on a resistive transistor (corresponding I

current characteristics de-

scribed in Figure 91). This data is based on characterization results, not tested in production.
6. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on
RESET pin with a duration below t

h(RSTL)in

can be ignored.

7. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
environments.
8. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device
can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Symbol

Parameter

Condit ions

Min

Typ

Max

Unit

Input low level voltage

0.3xV

Input high level voltage

0.7xV

hys

Schmitt trigger voltage hysteresis

400

Output low level voltage

(see Figure 92, Figure 93)

=5V

=+5mA

0.68

0.95

=+2mA

0.28

0.45

Weak pull-up equivalent resistor

=5V

=3.4V

100

120

w(RSTL)out

Generated reset pulse duration

External pin or
internal reset sources

1/f

SFOSC

h(RSTL)in

External reset pulse hold time

g(RSTL)in

Filtered glitch duration

100

RESET

WATCHDOG RESET

ST72XXX

LVD RESET

INTERNAL

0.1

4.7k

EXTERNAL

RESE T

CIRCUIT

RESET CONTROL

USER

ST72334J/N, ST72314J/N, ST72124J

132/148

15.11 COMMUNICATION INTERFACE CHARACTERISTICS

15.11.1 SPI - Serial Peripheral Interface

Subject to general operating conditions for V

OSC

, and T

unless otherwise specified.

Refer to I/O port characteristics for more details on
the input/output alternate function characteristics
(SS, SCK, MOSI, MISO).

Figure 95. SPI Slave Timing Diagram with CPHA=0

Notes:
1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends on the I/O port configuration.
3. Measurement points are done at CMOS levels: 0.3xV

and 0.7xV

Symbol

Parameter

Conditio ns

Min

Max

Unit

SCK

1/t

c(SCK)

SPI clock frequency

Master

CPU

=8MHz

CPU

/128

0.0625

CPU

MHz

Slave

CPU

=8MHz

CPU

r(SCK)

f(SCK)

SPI clock rise and fall time

see I/O port pin description

su(SS)

SS setup time

Slave

120

h(SS)

SS hold time

Slave

120

w(SCKH)

w(SCKL)

SCK high and low time

Master
Slave

100

su(MI)

su(SI)

Data input setup time

Master
Slave

100
100

h(MI)

h(SI)

Data input hold time

Master
Slave

100
100

a(SO)

Data output access time

Slave

120

dis(SO)

Data output disable time

Slave

240

v(SO)

Data output valid time

Slave (after enable edge)

120

h(SO)

Data output hold time

v(MO)

Data output valid time

Master (before capture edge)

0.25

CPU

h(MO)

Data output hold time

0.25

INPUT

SCK

INPUT

CPHA=0

MOSI

INPUT

MISO

OUTPUT

CPHA=0

c(SCK)

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

v(SO)

a(SO)

su(SI)

h(SI)

MSB OUT

MSB IN

BIT6 OUT

LSB IN

LSB OUT

see note 2

CPOL=0

CPOL=1

su(SS)

h(SS)

dis(SO)

h(SO)

see

note 2

BIT1 IN

ST72334J/N, ST72314J/N, ST72124J

133/148

COMMUNICATION INTERFACE CHARACTERISTICS (Cont'd)

Figure 96. SPI Slave Timing Diagram with CPHA=1

Figure 97. SPI Master Timing Diagram

Notes:
1. Measurement points are done at CMOS levels: 0.3xV

and 0.7xV

2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has
its alternate function capability released. In this case, the pin status depends of the I/O port configuration.

INPUT

SCK

INPUT

CPHA=0

MOSI

INPUT

MISO

OUTPUT

CPHA=0

w(SCKH)

w(SCKL)

r(SCK)

f(SCK)

a(SO)

su(SI)

h(SI)

MSB OUT

BIT6 OUT

LSB OUT

see

CPOL=0

CPOL=1

su(SS)

h(SS)

dis(SO)

h(SO)

see

note 2

c(SCK)

v(SO)

MSB IN

LSB IN

BIT1 IN

INPUT

SCK

INPUT

CPHA=0

MOSI

OUTPUT

MISO

INPUT

CPHA=0

CPHA=1

c(SCK)

w(SCKH)

w(SCKL)

h(MI)

su(MI)

v(MO)

h(MO)

MSB IN

MSB OUT

BIT6 IN

BIT6 OUT

LSB OUT

LSB IN

see note 2

CPOL=0

CPOL=1

CPOL=0

CPOL=1

r(SCK)

f(SCK)

ST72334J/N, ST72314J/N, ST72124J

135/148

15.12 8-BIT ADC CHARACTERISTICS

Subject to general operating conditions for V

, f

OSC

, and T

unless otherwise specified.

Figure 98. Typical Application with ADC

Notes:
1. Unless otherwise specified, typical data are based on T

=25

C and V

-V

=5V. They are given only as design guide-

lines and are not tested.
2. When V

DDA

and V

SSA

pins are not available on the pinout, the ADC refer to V

and V

3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10k

). Data

based on characterization results, not tested in production.
4. The stabilization time of the AD converter is masked by the first t

LOAD

. The first conversion after the enable is then

always valid.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

ADC

ADC clock frequency

MHz

AIN

Conversion range voltage

SSA

DDA

AIN

External input resistor

ADC

Internal sample and hold capacitor

STAB

Stabilization time after ADC enable

CPU

=8MHz, f

ADC

=4MHz

ADC

Convertion time (Sample+Hold)

- Sample capacitor loading time
- Hold conversion time

4
8

1/f

ADC

AINx

ST72XXX

~2pF

0.6V

AIN

DDA

SSA

0.1

ADC

ST72334J/N, ST72314J/N, ST72124J

136/148

8-BIT ADC CHARACTERISTICS (Cont'd)

ADC Accuracy

Figure 99. ADC Accuracy Characteristics

Notes:
1. ADC Accuracy vs. Negative Injection Current:
For I

INJ-

=0.8mA, the typical leakage induced inside the die is 1.6

A and the effect on the ADC accuracy is a loss of 1 LSB

for each 10K

increase of the external analog source impedance. This effect on the ADC accuracy has been observed

under worst-case conditions for injection:
- negative injection
- injection to an Input with analog capability, adjacent to the enabled Analog Input
- at 5V V

supply, and worst case temperature.

2. Data based on characterization results with T

=25

3. Data based on characterization results over the whole temperature range.

Symbol

Parameter

=5V,

CPU

=1MHz

=5.0V,

CPU

=8MHz

=3.3V,

CPU

=8MHz

Min

Max

Min

Max

Min

Max

Total unadjusted error

2.0

1.5

Offset error

1.5

Gain Error

1.5

Differential linearity error

1.5

Integral linearity error

1.5

1 LSB

IDEAL

1LS B

I DE AL

D D A

S SA

256

----------------------------------------

(LSB

IDEAL

)

(1) Example of an actual transfer curve
(2) The ideal transfer curve
(3) End point correlation line

=Total Unadjusted Error: maximum deviation

between the actual and the ideal transfer curves.
E

=Offset Error: deviation between the first actual

transition and the first ideal one.
E

=Gain Error: deviation between the last ideal

transition and the last actual one.
E

=Differential Linearity Error: maximum deviation

between actual steps and the ideal one.
E

=Integral Linearity Error: maximum deviation

between any actual transition and the end point
correlation line.

Digital Result ADCDR

255

254

253

253 254 255 256

(1)

(2)

(3)

DDA

SSA

ST72334J/N, ST72314J/N, ST72124J

137/148

16 PACKAGE CHARACTERISTICS

16.1 PACKAGE MECHANICAL DATA

Figure 100. 64-Pin Thin Quad Flat Package

Figure 101. 56-Pin Shrink Plastic Dual In-Line Package, 600-mil Width

Dim

inches

Min

Typ

Max

Min

Typ

Max

1.60

0.063

0.05

0.15 0.002

0.006

1.35 1.40 1.45 0.053 0.055 0.057

0.30 0.37 0.45 0.012 0.015 0.018

0.09

0.20 0.004

0.008

16.00

0.630

14.00

0.551

12.00

0.472

16.00

0.630

14.00

0.551

12.00

0.472

0.80

0.031

3.5

0.45 0.60 0.75 0.018 0.024 0.030

1.00

0.039

Number of Pins

Dim.

inches

Min

Typ

Max

Min

Typ

Max

6.35

0.250

0.38

0.015

3.18

4.95 0.125

0.195

0.41

0.016

0.89

0.035

0.20

0.38 0.008

0.015

50.29

53.21 1.980

2.095

15.01

0.591

12.32

14.73 0.485

0.580

1.78

0.070

15.24

0.600

17.78

0.700

2.92

5.08 0.115

0.200

Number of Pins

PDIP56S

ST72334J/N, ST72314J/N, ST72124J

138/148

PACKAGE MECHANICAL DATA (Cont'd)

Figure 102. 44-Pin Thin Quad Flat Package

Figure 103. 42-Pin Shrink Plastic Dual In-Line Package, 600-mil Width

Dim

inches

Min

Typ

Max

Min

Typ

Max

1.60

0.063

0.05

0.15 0.002

0.006

1.35 1.40 1.45 0.053 0.055 0.057

0.30 0.37 0.45 0.012 0.015 0.018

0.09

0.20 0.004

0.008

12.00

0.472

10.00

0.394

8.00

0.315

12.00

0.472

10.00

0.394

8.00

0.315

0.80

0.031

3.5

0.45 0.60 0.75 0.018 0.024 0.030

1.00

0.039

Number of Pins

Dim.

inches

Min

Typ

Max

Min

Typ

Max

5.08

0.200

0.51

0.020

3.05

3.81

4.57 0.120 0.150 0.180

0.46

0.56

0.018 0.022

1.02

1.14

0.040 0.045

0.23

0.25

0.38 0.009 0.010 0.015

36.58 36.83 37.08 1.440 1.450 1.460

15.24

16.00 0.600

0.630

12.70 13.72 14.48 0.500 0.540 0.570

1.78

0.070

15.24

0.600

18.54

0.730

0.00

1.52 0.000

0.060

2.54

3.30

3.56 0.100 0.130 0.140

Number of Pins

PDIP42S

ST72334J/N, ST72314J/N, ST72124J

141/148

16.4 PACKAGE/SOCKET FOOTPRINT PROPOSAL

16.4.1 User-supplied TQFP64 Adaptor / Socket

To solder the TQFP64 device directly on the appli-
cation board, or to solder a socket for connecting
the emulator probe, the application board should
provide the footprint described in Figure 106. This
footprint allows both configurations:

Direct TQFP64 soldering

YAMAICHI

IC149-064-008-S5*

socket

soldering to plug either the emulator probe or an
adaptor board with an TQFP64 clamshell
socket.
* Not compatible with TQFP64 package.

Figure 106. TQFP64 Device And Emulator Probe Compatible Footprint

Table 25. Suggested List of TQFP64 Socket Types

Package / Probe

Adaptor / Socket Reference

Socket type

TQFP64

ENPLAS

OTQ-64-0.8-02

Open Top

YAMAICHI

IC51-0644-1240.KS-14584

Clamshell

EMU PROBE

YAMAICHI

IC149-064-008-S5

SMC

DETAIL

* SK: Plastic socket overall dimensions.

Dim

inches

Min

Typ Max

Min

Typ Max

0.35 0.45 0.50 0.014 0.018 0.020

20.80

0.819

14.00

0.551

11.90 12.00 12.10 0.468 0.472 0.476

0.75 0.80 0.85 0.029 0.031 0.033

SK*

1.023

Number of Pins

64 (4x16)

E1
E3

SOCKET

ST72334J/N, ST72314J/N, ST72124J

142/148

PACKAGE/SOCKET FOOTPRINT PROPOSAL (Cont'd)

16.4.2 User-supplied TQFP44 Adaptor / Socket

To solder the TQFP44 device directly on the appli-
cation board, or to solder a socket for connecting
the emulator probe, the application board should
provide the footprint described in Figure 107. This
footprint allows both configurations:

Direct TQFP44 soldering

YAMAICHI IC149-044-*52-S5 socket soldering
to plug either the emulator probe or an adaptor
board with an TQFP44 clamshell socket.

Figure 107. TQFP44 Device And Emulator Probe Compatible Footprint

Suggested List of TQFP44 Socket Types

DETAIL

* SK: Plastic socket overall dimensions.

Dim

inches

Min

Typ Max

Min

Typ Max

0.35 0.45 0.50 0.014 0.018 0.020

13.40

0.527

10.00

0.394

7.95 8.00 8.05 0.313 0.315 0.317

0.75 0.80 0.85 0.029 0.031 0.033

SK*

24.2

0.953

Number of Pins

44 (4x11)

E1
E3

SOCKET

Package / Probe

Adaptor / Socket Reference

Socket type

TQFP44

ENPLAS

OTQ-44-0.8-04

Open Top

YAMAICHI

IC51-0444-467-KS-11787

Clamshell

TQFP44
EMU PROBE

YAMAICHI

IC149-044-*52-S5

SMC

ST72334J/N, ST72314J/N, ST72124J

143/148

17 DEVICE CONFIGURATION AND ORDERING INFORMATION

Each device is available for production in user pro-
grammable versions (FLASH) as well as in factory
coded versions (ROM). E

PROM data memory

and FLASH devices are shipped to customers with
a default content (FFh), while ROM factory coded
parts contain the code supplied by the customer.
This implies that FLASH devices have to be con-
figured by the customer using the Option Bytes
while the ROM devices are factory-configured.

17.1 OPTION BYTES

The two option bytes allow the hardware configu-
ration of the microcontroller to be selected.
The option bytes have no address in the memory
map and can be accessed only in programming
mode (for example using a standard ST7 program-
ming tool). The default content of the FLASH is
fixed to FFh.
In masked ROM devices, the option bytes are
fixed in hardware by the ROM code (see option
list).

USER OPTION BYTE 0

Bit 7:2 = Reserved, must always be 1.

Bit 1 = 56/42

Package Configuration.

This option bit allows to configured the device ac-
cording to the package.
0: 42 or 44 pin packages
1: 56 or 64 pin packages

Bit 0 = FMP

Full memory protection.

This option bit enables or disables external access
to the internal program memory (read-out protec-
tion). Clearing this bit causes the erasing (to 00h)
of the whole memory (including the option byte).
0: Program memory not read-out protected
1: Program memory read-out protected

Note: The data E2PROM is not protected by this
bit in flash devices. In ROM devices, a protection
can be selected in the Option List (see page 145).

USER OPTION BYTE 1

Bit 7 = CSS

Clock Security System disable

This option bit enables or disables the CSS fea-
tures.
0: CSS enabled
1: CSS disabled

Bit 6:4 = OSC[2:0]

Oscillator selection

These three option bits can be used to select the
main oscillator as shown in Table 26.

Bit 3:2 = LVD[1:0]

Low voltage detection selection

These option bits enable the LVD block with a se-
lected threshold as shown in Table 27.

Bit 1 = WDG HALT

Watchdog and halt mode

This option bit determines if a RESET is generated
when entering HALT mode while the Watchdog is
active.
0: No Reset generation when entering Halt mode
1: Reset generation when entering Halt mode

Bit 0 = WDG SW

Hardware or software watchdog

This option bit selects the watchdog type.
0: Hardware (watchdog always enabled)
1: Software (watchdog to be enabled by software)
Table 26. Main Oscillator Configuration

Table 27. LVD Threshold Configuration

Selected Oscillator

OSC2 OSC1 OSC0

External Clock (Stand-by)

~4 MHz Internal RC

1~14 MHz External RC

Low Power Resonator (LP)

Medium Power Resonator (MP)

Medium Speed Resonator (MS)

High Speed Resonator (HS)

Configuratio n

LVD1 LVD0

LVD Off

Highest Voltage Threshold (

4.50V)

Medium Voltage Threshold (

4.05V)

Lowest Voltage Threshold (

3.45V)

USER OPTIO N BYTE 0

USER OPTIO N BYTE 1

Reserved

56/42 FMP

CSS

OSC

LVD1 LVD0

WDG

HALT

WDG

Default

Value

ST72334J/N, ST72314J/N, ST72124J

144/148

DEVICE CONFIGURATION AND ORDERING INFORMATION (Cont'd)

17.1.1 Transfer Of Customer Code

Customer code is made up of the ROM contents
and the list of the selected options (if any). The
ROM contents are to be sent on diskette, or by
electronic means, with the hexadecimal file in .S19
format generated by the development tool. All un-
used bytes must be set to FFh.

The selected options are communicated to STMi-
croelectronics using the correctly completed OP-
TION LIST appended.

The STMicroelectronics Sales Organization will be
pleased to provide detailed information on con-
tractual points.

Figure 108. ROM Factory Coded Device Types

Figure 109. FLASH User Programmable Device Types

DEVICE PACKAGE

TEMP.

RANGE

XXX

Code name (defined by STMicroelectronics)

1 = standard 0 to +70

6 = industrial -40 to +85

7 = automotive -40 to +105

3 = automotive -40 to +125

B = Plastic DIP
T = Plastic TQFP

ST72334J2, ST72334J4, ST72334N2, ST72334N4,
ST72314J2, ST72314J4, ST72314N2, ST72314N4,
ST72124J2

DEVICE PACKAGE

TEMP.

RANGE

Code name (defined by STMicroelectronics)

1 = standard 0 to +70

6 = industrial -40 to +85

7 = automotive -40 to +105

3 = automotive -40 to +125

B = Plastic DIP
T = Plastic TQFP

ST72C334J2, ST72C334J4, ST72C334N2, ST72C334N4,
ST72C314J2, ST72C314J4, ST72C314N2, ST72C314N4,
ST72C124J2

XXX

ST72334J/N, ST72314J/N, ST72124J

145/148

ST72334/314/124 ROM MICROCONTROLLER OPTION LIST

Customer

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Address

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Contact

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Phone No

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Reference

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

STMicroelectronics references
Device:

[ ] ST72334J2 (8KB)

[ ] ST72314J2 (8KB)

[ ] ST72124J2 (8KB)

[ ] ST72334J4 (16KB)

[ ] ST72314J4 (16KB)

[ ] ST72334N2 (8KB)

[ ] ST72314N2 (8KB)

[ ] ST72334N4 (16KB)

[ ] ST72314N4 (16KB)

Package & Conditioning:

[ ] TQFP64

[ ] Tape and Reel

[ ]Tray

[ ] TQFP44

[ ] Tape and Reel

[ ]Tray

[ ] SDIP56
[ ] SDIP42

Marking:

[ ] Standard Marking
[ ] Special Marking

TQFP (max. 10 Chars. ): _ _ _ _ _ _ _ _ _ _
SDIP (max. 16 Chars. ): _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _

Authorized characters are letters, digits, `.', `-', `/' and spaces only.
Please consult your local STMicroelectronics sales office for other marking details if required.

Temperature Range:

[ ] 0

C to + 70

[ ] 0

C to + 85

[ ] - 40

C to + 85

[ ] - 40

C to + 105

[ ] - 40

C to + 125

Clock Source Selection:

[ ] Resonator:

[ ] LP: Low power resonator (1 to 2 MHz)
[ ] MP: Medium power resonator (2 to 4 MHz)
[ ] MS: Medium speed resonator (4 to 8 MHz)
[ ] HS: High speed resonator (8 to 16 MHz)

[ ] RC Network:

[ ] Internal
[ ] External

[ ] External Clock

Clock Security System:

[ ] Disabled

[ ] Enabled

Watchdog Selection:

[ ] Software Activation

[ ] Hardware Activation

Halt when Watchdog on:

[ ] Reset

[ ] No reset

Program Readout Protection:

[ ] Disabled

[ ] Enabled

Data E2PROM Readout Protection:

[ ] Disabled

[ ] Enabled

LVD Reset

[ ] Disabled

[ ] Enabled:

[ ] Highest threshold
[ ] Medium threshold
[ ] Lowest threshold

Comments :

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Supply Operating Range in the application: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Notes:

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ST72334J/N, ST72314J/N, ST72124J

146/148

17.2 DEVELOPMENT TOOLS

STMicroelectronics offers a range of hardware
and software development tools for the ST7 micro-
controller family. Full details of tools available for
the ST7 from third party manufacturers can be ob-
tain from the STMicroelectronics Internet site:

http//mcu.st.com.

Third Party Tools

ACTUM

COSMIC

CMX

DATA I/O

HITEX

HIWARE

ISYSTEM

KANDA

LEAP

Tools from these manufacturers include C compli-
ers, emulators and gang programmers.

STMicroelectronics Tools

Three types of development tool are offered by
ST, all of them connect to a PC via a parallel (LPT)
port: see Table 28 and Table 29 for more details.

Table 28. STMicroelectronic Tool Features

Table 29. Dedicated STMicroelectronics Development Tools

Note:
1. In-Situ Programming (ISP) interface for FLASH devices.

In-Circuit Emulation

Programming Capabili ty

Software Included

ST7 Development Kit

Yes. (Same features as
HDS2 emulator but without
logic analyzer)

Yes (DIP packages only)

ST7 CD ROM with:

ST7 Assembly toolchain
STVD7 and WGDB7 powerful

Source Level Debugger for Win
3.1, Win 95 and NT

C compiler demo versions
ST Realizer for Win 3.1 and Win

95.

Windows Programming Tools

for Win 3.1, Win 95 and NT

ST7 HDS2 Emulator

Yes, powerful emulation
features including trace/
logic analyzer

ST7 Programming Board No

Yes (All packages)

Suppor ted Products

ST7 Development Kit

ST7 HDS2 Emulator

ST7 Programming Board

ST72(C)334J2,
ST72(C)334J4,
ST72(C)334N2,
ST72(C)334N4,
ST72(C)314J2,
ST72(C)314J4,
ST72(C)314N2,
ST72(C)314N4,
ST72(C)124J2

ST7MDT2-DVP2

ST7MDT2-EMU2B

ST7MDT2-EPB2/EU

ST7MDT2-EPB2/US

ST7MDT2-EPB2/UK

ST72334J/N, ST72314J/N, ST72124J

148/148

Notes:

Information furnished is believed to be accurate and reliable. However, STMi croelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as criti cal components in life support devices or systems without the express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics

Purchase of I

C Components by STMicroelectronics conveys a license under the Philips I

C Patent. Rights to use these components in an

C system is granted provided that the system conforms to the I

C Standard Specification as defined by Philips.

STMi croelectronics Group of Companies

Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain

Sweden - Switzerland - United Kingdom - U.S.A.

http:// www.st.com

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ST72314J

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: ST72314J